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electronics excellence in low-power the way micom/dsp should be the way micom/dsp should be mar. 1999 KS32C5000(a)/ks32c50100 32- bit risc microcontroller for network solution
electronics contents n network protocol n what is network ? n osi reference model and tcp/ip n tcp/ip networking software & basic protocol n real-time operating system n real-time operating system n developping system with psosystem n psosystem bsp n developping system with nucleus n nucleus h/w device driver n applicable system with samsung ? s netmcu n managed hub n managed switching hub n router / layer-3 switching n printer server n network printer n cable modem n ups management controller
electronics 3 excellence in low-power the way micom/dsp should be net mcu system mcu what is network ? n network components l hosts ? any computing system that is attached to an internet l networks ? collection of two or more hosts that are interconnected using a particular form of data link technology l router ? the device that provides connectivity between the various indivisual networks n physical network technologies l local area network (lan) ? high speed, short distance ? ethernet, token ring, fddi l wide area network (wan) ? low speed, global networks, long distance ? x.25, isdn with hdlc
electronics 4 excellence in low-power the way micom/dsp should be net mcu system mcu osi reference model and tcp/ip n osi reference model l 7 layer for provides connectivity between the various indivisual networks n tcp/ip networking software l tcp/ip networking software provides a unified interface that is independent of the various indivisual networks physical layer data link layer network layer transport layer session layer presentation layer application layer ni (network interface) osi model layers mac(media access control) phy medium mii mdi ip (internet protocol) udp tcp socket & application layer s/w h/w
electronics 5 excellence in low-power the way micom/dsp should be net mcu system mcu tcp/ip networking software & basic protocol n network interface layer l h/w mac driver l arp (address resolution protocol) ? mapping internet address to physical network address l rarp (reverse address resolution protocol) ? obtain internet address from physical network address n ip (internet protocol) layer l routing, fragmentation, reassembly of datagrams l icmp protocol ? error report and network management tasks n transport layer l tcp (transmission control protocol) ? deliver packet by connection-oriented method l udp (user datagram protocol) ? deliver packet by connectionless method n socket layer l application programming interface n application layer l tftp, ftp, telnet, dns, nfs, rpc, smtp, snmp
electronics 6 excellence in low-power the way micom/dsp should be net mcu system mcu real-time operating system (rtos) n why we need rtos ? l task management l memory allocation l interrupt completion service l easy to develop application system that has network interface n what kind of rtos is supported for samsung ? s netmcu ? l psos + (isi) l nucleus (ati) n where can we get h/w device driver for rtos ? l samsung web-site : www. samsungsemi .com n how can we use the h/w device driver ? l after download the h/w device driver from samsung web site, you should extract and rebuild again for your purpose
electronics 7 excellence in low-power the way micom/dsp should be net mcu system mcu developping system with psosystem n psosystem components n psosystem debugging environments l s/w debugging environments ? probe + rom : target based debugger interface rom customer can get from samsung web site and isi ? prism + : debugger interface running on host system customer should pay charge to isi l h/w debugging environments ? embedded-ice customor can get from arm agent ? arm sdt(software development toolkit) customor can get from arm agent l psos + : single processor kernel l psos +m : multiprocessor kernel l probe + : target based debugger l phile + : file management l pna + : tcp/ip networking l ppp l prepc + : ansi c run-time library l drivers/board support package(bsp)
electronics 8 excellence in low-power the way micom/dsp should be net mcu system mcu psosystem bsp(board support package) disi serial driver probe + interface driver terminal driver slip/ppp probe + prepc + pna +(tcp/ip, udp) uart0 uart1 hdlca hdlcb mac ethernet driver net utility ( psh +, telnet, ftp) dram phile + ( ramdisk ) bsp n what is psosystem bsp(board support package) ? l h/w device driver for psos system ? timer ? serial driver (uart, hdlc) ? mac driver
electronics 9 excellence in low-power the way micom/dsp should be net mcu system mcu developping system with nucleus n nucleus components n nucleus debugging environments l s/w debugging environments ? udb not supported yet l h/w debugging environments ? embedded-ice customor can get from arm agent ? arm sdt(software development toolkit) customor can get from arm agent n supports l samsung : h/w device driver for nucleus l ati : all nucleus stack l application : application designer (customer side) l kernel l net4.0 : tcp/ip protocol stack l extended protocol package for nucleus net l ppp l file system
electronics 10 excellence in low-power the way micom/dsp should be net mcu system mcu l pmake nucleus h/w device driver serial driver terminal driver ppp net4.0(tcp/ip, udp) uart0 uart1 hdlca hdlcb mac ethernet driver net utility (tftp, telnet, ftp) dram ramdisk driver h/w device driver n h/w device driver for nucleus ? timer ? serial driver (uart, hdlc) ? mac driver
electronics 11 excellence in low-power the way micom/dsp should be net mcu system mcu applicable system with samsung ? s netmcu n managed hub n managed switching hub n router / layer-3 switching l modem router l ip router / ip sharing l isdn router l adsl router n printer server n network printer n cable modem n ups management controller
electronics 12 excellence in low-power the way micom/dsp should be net mcu system mcu network topology n network topology l the physical and/or electrical configuration of cabling and connections comprising a network -- the shape of the system. l bus, star, mesh, ring, star n star topology l most popular l each device has its own cable run connecting the device to a common hub or concentrator. only one device is permitted to use each port on the hub.
electronics 13 excellence in low-power the way micom/dsp should be net mcu system mcu single speed managed hub (10mbps) tp ports 10 m irb aui i/f serial management tp ports 10 m irb aui i/f serial management tp ports 10 m irb aui i/f serial management net mcu mac hdlc hdlc uart system manager 10 m 7-wire aui i/f console aui port boot rom dram 10 m 7-wire i/f phy ric ric ric 10 mbps only tp port
electronics 14 excellence in low-power the way micom/dsp should be net mcu system mcu single speed managed hub (100mbps) tp ports 100 m irb mii i/f serial management tp ports 100 m irb mii i/f serial management tp ports 100 m irb mii i/f serial management net mcu mac hdlc hdlc uart system manager console 100 mbps up-load tp port boot rom dram ric ric ric phy configuration mii port 100 m tp mii i/f 2 phy phy 100 mbps only tp port
electronics 15 excellence in low-power the way micom/dsp should be net mcu system mcu dual speed managed hub (10/100mbps) net mcu mac hdlc hdlc uart system manager console boot rom dram ric ric ric tp ports 10 m irb mii i/f 100 m irb serial management tp ports 10 m irb mii i/f 100 m irb serial management tp ports 10 m irb mii i/f 100 m irb serial management bridge chip mii i/f dram i/f mii i/f dram 10 mbps i/f 100 mbps i/f up/down selectable 10/100 tp port 10/100 mbps tp dual speed port
electronics 16 excellence in low-power the way micom/dsp should be net mcu system mcu managed switching hub (10/100mbps) net mcu mac uart system manager console boot rom dram switch controllr dram 10/100 mbps tp dual speed port phy(mii) i/f management quad mac switch engine phy(mii) i/f management quad mac switch engine phy(mii) i/f management quad mac switch engine quad phy quad phy quad phy up/down selectable 10/100 tp port system bus glue logic
electronics 17 excellence in low-power the way micom/dsp should be net mcu system mcu router n function l multiple lan users to access the internet simultaneously, using a single ip address through a 33.6k/56kb or isdn modems. l world wide web (www) for setup with your router l supports bootp/dhcp for automatic ip address assignment l standard 10/100 baset network interface with 4 port hub. n software for router l packet filtering l network address translation (nat) l ppp (pap/chap/lcp), ml-ppp l dynamic/static ip support l snmp l http l bootp/dhcp l tcp/ip stack ? udp ? tcp ? icmp ? arp/rarp l routing database l rip l dns resolver
electronics 18 excellence in low-power the way micom/dsp should be net mcu system mcu tp ports 10 m irb aui i/f net mcu mac uart system manager 10 m 7-wire aui i/f console boot rom dram 10 m 7-wire i/f phy 10 mbpstp port asynchronous modem router external uart (pc16x50) external i/o port external asynchronous modem rs232 i/f telephone line
electronics 19 excellence in low-power the way micom/dsp should be net mcu system mcu tp ports 10 m irb aui i/f net mcu mac hdlc hdlc uart system manager 10 m 7-wire aui i/f console boot rom dram 10 m 7-wire i/f phy 10 mbpstp port synchronous modem router v.35 i/f chip external synchronous modem v.35 i/f dsu/csu v.35 i/f t1/e1 line telephone line
electronics 20 excellence in low-power the way micom/dsp should be net mcu system mcu isdn reference model i s d n n e t w o r k l t e t n t 2 n t 1 t a t e 1 t e 2 r s t u u v 1 8 k f e e t p c / v . 3 4 m o d e m / f a x i s d n d e v i c e p b x e n d o f s e r v i c e p r o v i d e r ' s n e t w o r k - e u r o p e e n d o f s e r v i c e p r o v i d e r ' s n e t w o r k - n o r t h a m e r i c a isdn reference point v : proprietary interface within central office u : 2-wire interface up to 18k feets s/t : 4-wire interface up to 1k meters r : any non-isdn interface (rs-232, v.34) isdn reference equipment lt( line termination) : c.o switch or remote line card nt1/nt2(network termination) : cpe connection to network te1(terminal equipment type 1) : isdn compatable terminal te2(terminal equipment type 2) : non-isdn terminal ta (terminal adapter) : interface for non-isdn terminal
electronics 21 excellence in low-power the way micom/dsp should be net mcu system mcu isdn reference design (bri) u c h i p i d l s c p l t u c h i p i d l s c p l t s w i t c h i n g e q u i p m e n t u c h i p u c h i p g c i s / t c h i p i m p s c p i d l r o m r a m s / t c h i p c o d e c t e l e p h o n e n t 1 n t 1 / t e 1 c o d e c s c p i d l d d l c m p u s y s t e m i m p r o m r a m s / t c h i p c o d e c s c p i d l t e 1 t a t e l e p h o n e t e l e p h o n e imp : integrated multiprotocol processor idl : motorola interchip digital link scp : serial communication port
electronics 22 excellence in low-power the way micom/dsp should be net mcu system mcu isdn router (1 port) tp ports 10 m irb aui i/f net mcu mac hdlc hdlc uart system manager 10 m 7-wire aui i/f console boot rom dram 10 m 7-wire i/f phy 10 mbpstp port isdn s/t i/f chip codec handset telephone fax slic b2 d async . terminal v.120/x.25 external uart (pc16x50) external i/o port time solt assigner (epld) b1 2 b+1d isdn line
electronics 23 excellence in low-power the way micom/dsp should be net mcu system mcu isdn router (2 port) net mcu mac hdlc hdlc uart system manager 10/100 mii i/f 10/100 tp i/f console boot rom dram 10/100 m mii i/f phy isdn s/t i/f chip codec handset telephone fax slic b2 d async . terminal v.120/x.25 external uart (pc16x50) external i/o port time solt assigner (epld) b1 isdn line 2 channel hdlc controller isdn s/t i/f chip handset telephone fax 2 b+1d isdn line b2 d codec slic b1 control
electronics 24 excellence in low-power the way micom/dsp should be net mcu system mcu adsl router (type 1) net mcu mac hdlc hdlc uart system manager console boot rom dram adsl modem utopia interface 10/100 mii i/f 10/100 tp i/f 10/100 m mii i/f phy
electronics 25 excellence in low-power the way micom/dsp should be net mcu system mcu adsl router (type 2) net mcu mac uart system manager console boot rom dram adsl modem utopia interface 10/100 mii i/f 10/100 tp i/f 10/100 m mii i/f phy external i/o epld
electronics 26 excellence in low-power the way micom/dsp should be net mcu system mcu printer server (type 1) tp ports 10 m irb aui i/f net mcu mac system manager 10 m 7-wire aui i/f boot rom dram 10 m 7-wire i/f phy 10 mbpstp port printer serial /iee1284 external i/o port super-i/o sio pia iee1284 serial
electronics 27 excellence in low-power the way micom/dsp should be net mcu system mcu printer server (type 2) boot rom dram printer serial /iee1284 external i/o port super-i/o sio pia iee1284 serial 10/100 mii i/f 10/100 tp i/f 10/100 m mii i/f phy net mcu mac hdlc hdlc system manager sync/ async modem isdn modem glue logic telephone line isdn line printer server + router ? can be used as a router & printer server
electronics 28 excellence in low-power the way micom/dsp should be net mcu system mcu network printer net mcu mac system manager boot rom dram video controller arbiter bridge external i/o port 10/100 mii i/f 10/100 tp i/f 10/100 m mii i/f phy shared sram engine controller print module motor rom dram
electronics 29 excellence in low-power the way micom/dsp should be net mcu system mcu network mfp (multi-function printer) boot rom dram external i/o port 10/100 mii i/f 10/100 tp i/f 10/100 m mii i/f phy net mcu mac hdlc hdlc system manager sync. modem isdn modem interface glue logic printer fax copy machine arbiter bridge shared sram telephone line isdn line
electronics 30 excellence in low-power the way micom/dsp should be net mcu system mcu cable modem net mcu mac uart system manager 10/100 mii i/f 10/100 tp i/f console boot rom dram 10/100 m mii i/f phy handset telephone dsp codec slic external i/o port cable mac 64/256 qam qpsk/ 16 qam rf if. sram cable interface
electronics 31 excellence in low-power the way micom/dsp should be net mcu system mcu ups management controller net mcu mac uart system manager 10/100 mii i/f 10/100 tp i/f boot rom dram 10/100 m mii i/f phy hub management monitor uart ups ( uninterruptible power supplies ) ups management controller ? collect ups/power status information ? reliable shootdown /reboot ? monitoring power consumption
a a a a KS32C5000(a) interface 1 0.0 arm7s boa rd b 1 1 friday, april 09, 1999 title size document number rev date: sheet of xdata7 xdata6 xdata5 xdata4 xdata3 xdata2 xdata1 xdata0 add r2 add r1 add r0 res et no e nwb e0 nec s0 euartin t eu arttx euartrx neu artdsr neuartdtr neu artrts neu artcts neuartcd xeu arttxd xe uartrxd nxe uartdtr nxeu artdsr nxeua rtrts nxeua rtcts nxe uartcd xdata[7..0] addr[2..0] nwbe[3..0] vdd_5 vdd_ 5 vdd_ 5 r? 1m u? st16c5 50 16550 ( 44pin plcc ) d0 2 d1 3 d2 4 d3 5 d4 6 d5 7 d6 8 d7 9 a0 31 a1 30 a2 29 res et 39 ni ow 20 ni or 24 cs0 14 cs1 15 ncs2 16 in t 33 tx 13 ndtr 37 nrts 36 rx 11 ndsr 41 ncts 40 ncd 42 nri 43 rclk 10 baudout 17 nop1 38 nop2 35 ior 25 iow 21 nddis 26 nas 28 ntxrdy 27 nrxrdy 32 xtal1 18 xtal2 19 nc1 1 nc12 12 nc23 23 nc34 34 vcc44 44 gnd22 22 y? 1.8432mhz c? 27pf c? 27pf u? max232 c1 + 1 c1- 3 c2 + 4 c2- 5 t1o 14 r1i 13 t2o 7 r2i 8 vcc 16 v+ 2 v- 6 gnd 15 t1i 11 r1o 12 t2i 10 r2o 9 c? 0.1uf + c? 0.1uf + c? 0.1uf + c? 0.1uf + c? 0.1uf + u? max232 c1 + 1 c1- 3 c2 + 4 c2- 5 t1o 14 r1i 13 t2o 7 r2i 8 vcc 16 v+ 2 v- 6 gnd 15 t1i 11 r1o 12 t2i 10 r2o 9 c? 0.1uf + c? 0.1uf + c? 0.1uf + xdata[31..0] addr[21..0] res et no e nwbe[3..0] nec s0 euartin t
a a a a cr ad dress setting on : 3f0h off: 250h ( bios address default ) half to extern al interrupt this port should be set to proper use necs0 xdata 0 xdata 1 xdata 2 xdata 3 xdata 4 xdata 5 xdata 6 xdata 7 reset addr0 addr1 addr2 addr3 addr4 addr5 addr6 addr7 addr8 addr9 addr10 hefras vcc vcc vc c vc c vc c vcc vc c c88 0.1uf + l7 l3216 y2 14.318mhz nc 1 gnd 2 vcc 4 out1 3 r10 7 4.7k r10 9 4.7k r11 0 4.7k r11 1 4.7k r11 2 4.7k r11 3 4.7k r11 4 4.7k u? w83877tf cs# 2 a0 51 a1 52 a2 53 a3 54 a4 55 a5 57 a6 58 a7 59 a8 60 a9 61 a10 75 d0 66 d1 67 d2 68 d3 69 d4 70 d5 71 d6 72 d7 73 mr 6 ae n 62 iochrdy/ple d 5 ior # 63 iow# 64 t/c 97 irqc/irq 3 44 irqd/irq 4 37 irqf/irq6 99 irqe/irq 7 23 drq a/drq1 39 dacka#/dack1# 41 drqb/drq2 100 dackb#/dack 2# 98 drqc/dr q3 4 dackc#/da ck3# 18 clki n 7 smi# 8 irqa/ gio1 96 irq b/gio0 92 irqg/pcicl k 1 irqh/ser irq 91 irrx 2 94 irtx2 95 ir qin 93 sci# 3 rw c# 87 inde x# 81 moa# 79 dsb # 84 dsa# 83 mo b# 80 di r# 89 step# 82 wd # 86 we # 85 trak0# 78 wp # 77 rdata# 74 he ad# 88 ds kchg# 76 ctsa# 34 dsra# 33 dcda# 32 ria# 31 sina 30 souta/penfdc 38 dtra#/hefras 35 rtsa#/ppnpcvs 36 ctsb# 47 dsrb# 48 dcdb# 49 rib# 50 sinb 42 soutb/psmisci 43 dtrb#/penpll 46 rtsb#/pgoiqsel 45 err# 29 ack# 26 busy 24 pe 27 slct 28 slin# 22 init# 21 afd# 20 stb# 19 pd3 12 pd4 13 pd5 14 pd6 16 vcc 15 vcc 56 vss 25 vss 40 vss 65 vss 90 pd0 9 pd1 10 pd2 11 pd7 17 r10 8 4.7k r10 4 4.7k r10 5 4.7k r10 6 4.7k r10 3 4.7k r10 6 4.7k r11 5 4.7k addr[21:0 ] necs 0 xdata[31:0] rese t nwbe 0 ir q_uart noe souta ctsa dsra dc da ria sina dt ra rtsa
a a a a gnd_r gnd_t p hy clock osc 25 mhz * sette d to phy id #1 - p0ac : phy id0/activity led * led status - p1cl : phy id1/c ollision detected - p2li : phy id2/l ink integrity led - p3td : phy id3/ transmit data led - p4rd : phy id4 /receive data led configured as your purp ose 1 0.0 arm7s boa rd b 1 1 friday, april 09, 1999 title size document number rev date: sheet of ref_in nod/rep 10/100sel nitcls mii/si hw/sw dpxse l 10/lp ansel tptri rxtri p0ac p1cl p2li p3td p4rd rxd3 rxd2 rxd1 rxd0 tx d0 tx d1 tx d2 tx d3 p0ac p1cl p2li p3td p4rd vc c vc c vc c_r vcc_ t vc c vc c vcc r3 9 1.5k 1 2 r6 4 2.4k 1 2 r6 5 6.81k 1 2 r5 3 33 1 2 r5 2 33 1 2 r4 9 33 1 2 r4 5 33 1 2 r4 4 33 1 2 r4 6 33 1 2 r5 1 33 1 2 r6 1 33 1 2 r6 0 33 1 2 r5 8 33 1 2 r5 6 33 1 2 r5 5 33 1 2 r5 7 33 1 2 r5 9 33 1 2 r6 3 33 1 2 r6 2 33 1 2 c3 0.1uf + 1 2 c4 10uf + 1 2 c11 0.1uf + 1 2 c12 10uf + 1 2 r33 110 1 2 r3 7 49.9 1 2 r36 49.9 1 2 c7 0.1uf + 1 2 r3 2 50 1 2 r3 4 50 1 2 r3 5 50 1 2 c5 0.01uf + 1 2 r48 50 1 2 r4 2 50 1 2 r4 1 50 1 2 c1 0 0.01uf + 1 2 c8 0.1uf + 1 2 u5 ics18 90 phy nod/ rep 1 10/100se l 2 10tcsr 3 100tcsr 4 tp_tx+ 5 tp_tx- 6 vss_7 7 vdd_8 8 tp tri 9 tp_rx+ 10 tp_rx- 11 nc_12 12 itcls 13 nc_14 14 nc_15 15 vdd_16 16 vss_17 17 vdd_18 18 mii/si 19 reg 20 lsta 21 res et 22 hw /sw 23 dpxsel 24 vdd_25 25 nc_26 26 lo ck 27 10/l p 28 vss_29 29 md io 30 md c 31 rxd3 32 rxd2 33 rxd1 34 rxd0 35 rxdv 36 rx clk 37 rx er 38 rxtr i 39 vss_40 40 vdd_41 41 txe r 42 txc lk 43 txe n 44 tx d0 45 tx d1 46 tx d2 47 tx d3 48 col 49 cr s 50 vss_51 51 ref_o ut 52 ref _in 53 vdd_54 54 vss_55 55 vdd_56 56 vdd_57 57 p0a c 58 p1cl 59 p2li 60 p3t d 61 p4 rd 62 vss_63 63 anse l 64 r4 7 75 1 2 c9 0.1uf + 1 2 r3 1 75 1 2 u6 pe6 8517 td+ 1 td- 2 ct_3 3 cmt_6 6 tx- 7 tx+ 8 rd - 16 rd+ 15 ct_14 14 cmt_ 11 11 rx+ 10 rx- 9 nc_4 4 nc_ 13 13 j9 rj 45 tx+ 1 tx- 2 rx + 3 p4 4 p5 5 rx- 6 p7 7 p8 8 u4 osc nc 1 gnd 1 4 gnd 2 7 out2 8 out1 11 vcc 14 r3 0 22 1 2 c6 0.1uf + 1 2 l3 l3216 1 2 r3 8 1k 1 2 d11 le d 1 2 d12 le d 1 2 d13 le d 1 2 d14 le d 1 2 d15 le d 1 2 r4 0 1k 1 2 r4 3 1k 1 2 r5 0 1k 1 2 r5 4 1k 1 2 nreset md io md c rxd[3: 0] rxdv rxc lk rxe r txcl k co l crs txd[3:0] txe n txe r
a a a a magneytic rj45 twist-pair interface magneytic aui port aui interface 1 0.0 arm7s boa rd b 1 1 saturday, april 10, 1999 title size document number rev date: sheet of ledl led t le dr le dc vc c vc c vcc vcc r3 8 4.7k r49 4.7k r4 3 12.4kr/1% r4 4 510 r3 7 4.7k r47 4.7k r42 510 c31 0.1uf r46 4.7k r4 5 4.7k r3 6 4.7k r3 9 4.7k r4 0 510 r48 4.7k r4 1 510 l1 l3216 r51 4.7k u5 lxt901a lxt 901 a/907a vcc1 10 cip 11 cin 12 nt h 13 md0 14 md1 15 li 19 jab 21 test 22 tc lk 23 tx d 24 te n 25 clko 26 cl ki 27 co l 28 autos el 29 le dr 34 ledt/pdn * 35 ledl 36 ledc/fde * 37 lbk 38 gnd1 39 rbias 42 gnd a 40 rxd 45 cd 46 rc lk 47 vcca 9 plr 52 tpopb 53 tpopa 54 gnd2 55 vcc2 56 tpona 57 tponb 58 ut p/stp* 59 tpip 61 tpin 62 pa ui 3 dip 4 din 5 dop 7 don 8 nc 1 nc 2 nc 6 nc 16 nc 17 nc 18 nc 20 nc 30 nc 31 nc 32 nc 33 nc 43 nc 41 nc 44 nc 48 nc 49 nc 50 nc 51 nc 60 nc 63 nc 64 y? 20mh z c? 27pf c? 27pf d5 le d d4 le d d3 le d d2 le d r8 330 r9 330 r10 330 r11 330 r? 50 r? 50 c? 0.1uf r? 24.9/1% r? 24.9/1% r? 78 r? 78 r? 78 txd[0](txd _10m) txd[1](loop _10m) tx_en( txen_10m) tx_clk(txclk _10m) rx_clk(rxcl k_10m) rxd[0](rx d_10m) crs(cr s_10m) col(col_ 10m)
a a a a rj45 for adaptor l eds : 100mbps le dr : receiver ledt : transmitter ledl : 100mbps(idle) 10mbps(link) led c : collision leds ledc ledl ledt ledr 1% 1% 1% p hy clock osc 1 0.0 arm7s boa rd b 1 1 friday, april 09, 1999 title size document number rev date: sheet of gndt vcct gndt rxer gndr gndt vccr gndr vcct gndt phy_clk phy_clk mdio mdc col crs nreset tx d0 tx d1 tx d2 tx d3 txe n txc lk tx er rxclk rxdv rxd3 rxd2 rxd1 rxd0 vd dd vd dd vd dd vd dd vd dd d5 le d d4 le d d3 led d2 le d d1 le d r7 680 r8 680 r1 7 100 c26 0.1uf c25 0.1uf l1 f.b. l2 f.b. r1 8 1k r1 9 2k c2 2 0.001uf/2kv j1 xfatm2-com bo-4 cm t 1 ct_t 2 tx+ 3 tx- 4 nc 5 ct_ r 6 rx + 7 rx- 8 c2 1 0.1uf c2 7 0.1uf r9 680 r1 0 680 r11 680 r5 9 1k d2 7 le d r13 49.9 r1 4 49.9 r1 5 22k 1% c3 0 0.1uf l3 f.b. l4 f.b. c2 8 10uf + c23 10uf + c2 4 10uf + c2 0 0.1uf r20 10k u4 lev elone col 64 txc lk 57 tx d3 62 tx d2 61 tx d1 60 tx d0 59 txe n 58 txe r 56 cr s 1 rx clk 54 rxd3 47 rxd2 48 rxd1 49 rxd0 50 rxdv 51 rx er 55 md c 45 md io 44 nreset 16 leds 38 le dc 39 ledl 40 led t 41 le dr 42 xi 12 x0 11 pwrdwn 34 vddd 9 vddo 53 mdint 2 gn dd 43 gnd o 52 test 10 mf0 8 mf1 7 mf2 6 mf3 5 mf4 4 fib p 27 fib n 28 fibop 17 fibon 18 rbias 25 tref 20 tpop 21 tpon 23 trip 29 trin 30 vcct 19 gndt 22 vcca 24 gnda 26 vccr 37 gndr 31 r2 1 22 l5 f.b. u5 osc(25mh z) nc 1 vdd 8 gnd 4 out 5 c3 1 0.1uf txd[0..3] rxd[0..3] rx clk co l txe n txe r md io rxdv rx er crs txcl k nreset md c
a a a a 25m hz : phy clock port5 is phy mode serial clock receive chip id is 0 not used redundant power not used up : l ocal manager not present down : local manager present(will be used) arb itration chain based ir100data[4..0] rx d0 rx d2 rx d3 txd 3 txd 0 txd 2 txd 1 rx d1 rbias vccv vcc t vc cr gnd t gndv gnd t gn dr gnda le dsel0 le dsel1 link led1 spdled 1 link led2 spdled 2 link led3 spdled 3 link led4 spdled 4 link led5 rcv led5 spdled 5 col1 0led col10 0led mg rled act10 led act100 led fault led rcv led1 rcv led2 rcv led3 rcv led4 le dsel1 le dsel0 hold col mmst rin mmstr out arbin arbout ir10iso nir10c fsbp nir10c fs nir10co lbp nir10col nir10ena nir10 den ir10c lk ir10data nir100c fsbp nir100sngl nir100 den nir100dv ir100data0 ir100data1 ir100data2 ir100data3 ir100data4 ir100c lk ir100iso hold col mmst rin mmstr out arbin arbout nir100c fs nir100col link led1 spdled 1 link led2 spdled 2 link led3 spdled 3 link led4 spdled 4 col1 0led col10 0led act10 led act100 led fault led rcv led1 rcv led2 rcv led3 rcv led4 vdd_ 5 vdd_ 5 vdd_ 5 vdd_ 5 vdd_ 5 vdd_ 5 vcc_v vcc_ t vcc _r gnd_ t gnd_v gnd_a gnd _r gnd_ t gnd_ t gnd _r gnd_ t gnd _r gnd_ t gnd _r gnd_ t gnd _r vdd_ 5 vdd_ 5 vdd_ 5 vdd_ 5 vdd_ 5 vdd_ 5 r? 22 l? f.b. u? osc 25mhz nc 1 vdd 8 gn d 4 out 5 c? 0.1uf u? lxt980 lxt980 port 1_spd0 189 port 1_spd1 188 port 2_spd0 187 port 2_spd1 186 port 3_spd0 185 port 3_spd1 184 port 4_spd0 183 port 4_spd1 182 por t5_spd 100 port5 _sel 99 confi g0 197 confi g1 196 confi g2 195 confi g3 194 confi g4 193 confi g5 192 confi g6 191 confi g7 190 mii_r xd2 32 mii_r xd3 33 mii_rx dv 26 mii_rx clk 25 mii_ rxer 24 mii_r xd0 29 mii_r xd1 30 mii_t xer 22 mii_tx clk 21 mii_t xen 20 mii_tx d0 19 mii_tx d1 18 mii_tx d2 17 mii_tx d3 16 mii_c ol 14 mii_ crs 13 mmst rin 199 mmstr out 63 nir100c fs 36 nir100c fsbp 37 nir100sngl 38 nir100col 40 nir100 den 41 nir100dv 42 ir100dat0 43 ir100dat1 44 ir100dat2 45 ir100dat3 46 ir100dat4 49 ir100c lk 52 ir100iso 56 ir10dat 9 ir10c lk 10 nir10 den 6 nir10ena 8 nir10col 3 nir10co lbp 4 nir10c fs 1 nir10c fsbp 5 macacti ve 79 ir10iso 55 hold col 80 tpop1 149 tpon1 151 tpop2 136 tpon2 138 tpop3 121 tpon3 123 tpop4 108 tpon4 110 tpip1 146 tpin1 147 tpip2 133 tpin2 134 tpip3 118 tpin3 119 tpip4 105 tpin4 106 fibop1 153 fibon1 154 fibop2 140 fibon2 141 fibop3 125 fibon3 126 fibop4 112 fibon4 113 fibip1 157 fibin1 156 fibip2 144 fibin2 143 fibip3 129 fibin3 128 fibip4 116 fibin4 115 sigdet1 155 sigdet2 142 sigdet3 127 sigdet4 114 rec onfig 58 ser_m atch 62 sr x 59 stx 60 se rclk 61 arbin 198 arbout 64 arbs elect 65 nmgr _pres 66 ledsel0 208 ledsel1 207 port1_led1 181 port2_led1 177 port3_led1 173 port4_led1 166 port5_led1 162 port1_led2 180 port2_led2 176 port3_led2 172 port4_led2 165 port5_led2 161 port1_led3 179 port2_led3 175 port3_led3 171 port4_led3 164 port5_led3 160 col10_led 85 col100_led 86 mgr_led 87 act10_led 90 act100_led 91 fauld_led 92 rps_led 98 nre set 53 clk2 5 54 ch ipid0 71 ch ipid1 72 ch ipid2 73 nirq 81 vcc1 2 12 vccr1 07 107 vccr1 20 120 vccr1 35 135 vccr1 48 148 vcct11 1 111 vcct12 4 124 vcct13 9 139 vcct15 2 152 vccv94 94 vccv169 169 vcc2 8 28 vcc3 5 35 vcc5 1 51 vcc5 7 57 vcc7 6 76 vcc8 4 84 vcc8 9 89 vcc9 6 96 vcc17 0 170 vcc20 1 201 vcc20 3 203 vcc20 6 206 gndt109 109 gndt122 122 gndt137 137 gndt150 150 gndr104 104 gndr117 117 gndr132 132 gndr145 145 gnda27 27 gnda130 130 rbias 131 gndv95 95 gndv168 168 gnd2 2 gnd11 11 gnd34 34 gnd50 50 gnd74 74 gnd75 75 gnd82 82 gnd83 83 gnd88 88 gnd93 93 gnd158 158 gnd159 159 gnd163 163 gnd167 167 gnd174 174 gnd178 178 gnd200 200 gnd202 202 rps_pres 78 nrps_fault 77 prom_clk 67 prom_cs 68 prom_dtout 69 prom_dtin 70 nc7 7 nc15 15 nc23 23 nc31 31 nc39 39 nc47 47 nc48 48 nc97 97 nc101 101 nc102 102 nc103 103 r? 4.7k r? 4.7k r? 4.7k r? 4.7k r? 4.7k r? 4.7k r? 4.7k r? 4.7k r? 4.7k r? 4.7k r? 200 r? 200 r? 200 r? 200 r? 200 r? 200 r? 200 r? 200 r? 200 r? 200 r? 200 r? 200 r? 200 r? 200 r? 200 r? 200 r? 1k r? 1k r? 4.7k r? 680 r? 330 r? 182 d? le d d? le d d? le d d? le d d? le d d? le d d? le d d? le d d? le d d? le d d? le d d? le d r? 330 r? 330 r? 330 r? 330 r? 330 r? 330 r? 330 r? 330 r? 330 r? 330 r? 330 r? 330 d? le d d? le d d? le d d? le d d? le d nrst por t_spd1 por t_spd0 tx cb tx db rx db rxd[0..3] txd[0..3] rxd v rxc lk txc lk rxer tx er co l crs tx en mmst rin hold col mmstr out arbin arbout ir100data[4..0] nir100c fs nir100c fsbp ir100c lk nir100col nir100dv ir100iso nir100 den nir100sngl ir10data nir10c fs nir10c fsbp ir100c lk nir10col ir10iso nir10 den nir10co lbp nir10ena
ks32c50100/5000a risc microcontroller a bout snds100 board 1- 1 1 about snds100 board system overview snds100(samsung netarm development system for ks32c50100/KS32C5000(a) is a platform that is suitable for code development of samsung's ks32c50100 16/32-bit risc microcontroller( netarm-ii) for ethernet-based system. also it supports a development of KS32C5000(a)( netarm-i) in a similar way as snds do. ks32c50100/KS32C5000(a) consists of 16-/32-bit risc(arm7tdmi) cpu core, 8-kbyte unified cache/sram, i2c-bus controller, ethernet controller with 2-channel buffered dma, 2 hdlc with 4-channel buffered dma, 2- channel gdma, 2 uarts, two 32-bit timers, 18 programmable i/o ports, interrupt controller, and a system manager. it also supports jtag boundary scan for the application system testing. snds100 consists of ks32c50100/KS32C5000(a) , boot eeprom(flash rom), dram module, sdram, serial ports for console, two serial communication ports, ethernet interface, configuration switches, and status leds/lcd. the ethernet interface has a complete ieee802.3 physical layer interface with ethernet hub/router side rj45 connector configuration. snds100 board overview the snds100 shows the basic system-based hardware design which uses the ks32c50100/KS32C5000(a) . it can evaluate the basic operations of the ks32c50100/KS32C5000(a) and develop codes for it as well. when the ks32c50100/KS32C5000(a) is contained in the snds100 , you can use an in-circuit emulator(ice). this allows you to test and debug a system design at the processor level. in addition, the ks32c50100/ KS32C5000(a) with embeddedicetm capability can be debugged directly using the embeddedice interface. the snds100 function blocks are shown in figure 1-1.
about snds100 board ks32c50100/500 0a risc microcontroller 1- 2 arm7tdmi 32bit risc cpu cpu i/f 8-kbyte unified cache/sram iic bus router 18 general i/o ports 4-word write buffer ice breaker interrupt controller uart 0,1 32-bit timer0,1 gdma 0,1 pll memory controller with refresh control system bus arbitor 2-ch hdlc with dmas ethernet controller buffered dma tx buffer(256bytes) rxbuffer(256bytes) cam(128 bytes) mac tx fifo (80 bytes) rx fifo (16 bytes) tap controller for jtag netmcu boot rom (rom bank 0) edo/sdram (dram bank 0) lcd driver (ext. i/o 0) serial comm i/f ethernet phy i/f (mii/7-wire) embedded ice i/f iic serial eeprom status control s/w uart console figure 1-1. snds100 block diagram
ks32c50100/5000a risc microcontroller a bout snds100 board 1- 3 features ? ks32c50100/ks32 c5000(a) : 16/32-bit risc microcontroller ? boot rom : 512k bit, 1m bit, 4m bit, support byte, half-word, word size boot rom ? dram : 72-pin simm module with two banks and edo dram support ? sdram : two 4mx16 with 2banks sdram support ? external i/o : status lcd driver ? general i/o : control switches and status display led ? two serial ports, one for console ? i2c-bus eeprom ? two-channel serial communication interface ? 10/100mbps ethernet interface ? embeddedice tm interface figure 1-2. snds100 rev1.0 evaluation board
about snds100 board ks32c50100/500 0a risc microcontroller 1- 4 circuit description snds100 board consists of logic components, several control/status display block, and a debug interface block. snds100 board's detailed block diagram, and its components are shown in figure 1-4. snds100 board schematics are inserted at the end of this section. power supply snds100 is designed to operate at 3.3v and 5v. power to the snds100 is supplied through a dc jack power adapter which supports the voltage between 6v and 9v and drives the current at least 850 ma . snds100 board has distributed power plane, with power going separately to the mcu and the main power plane. in case of KS32C5000(a), main power and mcu power has 5v level. but with ks32c50100,mcu power has 3.3v. for this reason, power jumpers j5,j6,j7 and j8 are inserted ( see figure 1-3 ) . dc jack regulator regulator netmcu (ks32c50100/ KS32C5000(a)) j5 j6 j7 j8 1 2 3 5v 3.3v mcu power snds100 peripheral i/o devices u26 u27 +6v ~ + 9v above 850ma gnd j5 j6 j7 j8 1 2 3 j5 j6 j7 j8 1 2 3 j5 j6 j7 j8 1 2 3 5v 3.3v mcu power (a) KS32C5000(a) (b) ks32c50100 (c) snds100 power plane (d) dc power adaptor figure 1-3. snds100 power plane
ks32c50100/5000a risc microcontroller a bout snds100 board 1- 5 arm7tdmi (netmcu) KS32C5000(a)/ks32c50100 probe connector probe connector probe connector probe connector flash (boot rom) rom bank1, 8,16bytes dram (72pin simm) dram bank0 sdram dram bank0 addr[21:0] xdata[31:0] rom0 signal dram0 signal sdram0 signal dsub9(2-ch) dsub 25(2-ch) sp232acn sp232acn hdlc i/f signal uart i/f signal jtag port iic eeprom iic i/f signal jtag i/f signal dc power input (6~9v,+850ma) regulator (3.3v,5v) 5v peripheral power 3.3v,5v cpu power phy mii or 7-wire i/f adaptor side connection configuration ethernet control status led 25mhz osc. station mangement system osc. 10mhzor 33mhz led for cpu status p[7:0] lcd display necs0 xdata[7:0] control switch magnetic rj45 figure 1-4. detailed snds100 board diagram
about snds100 board ks32c50100/500 0a risc microcontroller 1- 6 clock source and distribution the following clock sources are supported at snds100 target board. system clock (mclk) in case of that the attached device on snds100 is KS32C5000(a), then you can use 33mhz oscillator for system clock source. if ks32c50100 device is attached on it, then you can directly assign the 50mhz oscillator to the mclk input pin or 10mhz with pll enabled. (see, figure 1-5) system clock out (mclko) mclko is the same signal as internal system clock(mclk) of ks32c50100/5000(a). this clock can be monitored at mclko pin as to assign high to clkoen(mcko clock output enable/disable input) pin . if you want to use sdram with ks32c50100, mclko should be used. (see, figure 1-5) table 1-1. system clock configurations device jumper 1-2(high) 2-3(low) note ks32c50100/ KS32C5000(a) tmod(j2) (don ? t use) normal should be set to low for normal operation. KS32C5000(a) mclk/2 mclk system clock(mclk) select input pin. ks32c50100 clksel(j3) mclk pll output mclk input frequency can be controlled by this pin. ks32c50100/ KS32C5000(a) clkoen(j4) mclko enabled mclko disabled mclko have to be enabled to use sdram(only for ks32c50100) KS32C5000(a) (a) use mclk(33mhz) (b) use mclk/2 (c) don't use ks32c50100 (a) use pll(10mhz osc) (c) use 50mhz osc (c) use pll & sdram j2 j3 j4 1 2 3 j2 : tmod j3 : clksel j4 : clkoen j2 j3 j4 1 2 3 (a) j2 j3 j4 1 2 3 (b) j2 j3 j4 1 2 3 (c) figure 1-5. the examples of system clock(mclk) configurations
ks32c50100/5000a risc microcontroller a bout snds100 board 1- 7 ethernet control clock 25mhz crystal oscillator have to be used for 100/10mbps ethernet phy control clock. external uart clock ks32c50100/5000a support the external uart clock input pin (uclk[64]). if you using KS32C5000 with snds100, this uclk input pin have to be assigned to low. because it is used as the test mode selection pin(tmod1) for KS32C5000. (see figure 1-6). j11 from osc (29.4912mhz) uclk/tmode1 (a) enable external uart clock for KS32C5000a/50100 j11 from osc (29.4912mhz) uclk/tmode1 (b) disable external uart clock for KS32C5000 figure 1-6. external uart clock configurations reset logic the nreset(system reset signal) must be held to low level at least 540 master clock cycles to reset a ks32c50100/5000(a). nreset and ntrst(jtag reset signal) is logic anded. but, if you want to use circuit emulator(ex, embedded ice) for dubug without boot rom, you should have the ntrst is floated. if not, whenever the adw(arm debug window) were invoked sw interrupt will be occurred. therefore, the current snds100 rev.1.0 schematic for reset logic have to be updated. it is referred to ? section 4. jtag for embedded ice interface ? . snds100 system configurations snds100 board provides big-/little- endian mode with ks32c50100/5000a and supports byte/ halfword/word access the data bus. are you using KS32C5000(a) on snds100 board?. then you have to pull-out the all jumper from j9. because of these pins are cpu monitoring pins(cpump[2:0]) of KS32C5000(a). but, in case of ks32c50100, these pin functions are changed to the filter input and analog power for the internal pll circuit. see the schematic file which is at the end of this section.
about snds100 board ks32c50100/500 0a risc microcontroller 1- 8 flash boot rom dip type rom sockets(u17, u18) are on snds100 for to support the byte(8 bits) or halfword(16 bits) boot rom even though the data bus for rom bank0 can be configured by b0size[1:0] pins up to 32bit. s6 on 1 2 3 4 8 7 6 5 b0size1 b0size0 little s6 on 1 2 3 4 8 7 6 5 nc(not used) configuration example for 16bit boot rom, big endian mode b0size1 : off b0size0 : on little : off figure 1-7. snds100 board configurations table 1-2. rom bank0 data bus width pin functions s6: b0size[1:0] pin value descriptions rom bank0 on, on ? 00 ? reserved data bus width on,off ? 01 ? byte (8 bits) configuration off,on ? 10 ? half-word (16 bits) off,off ? 11 ? word (32 bits) table 1-3. endian mode configuration pin functions s6: little pin value descriptions endian mode on ? 1 ? little endian mode (ks32c50100/KS32C5000a) selection off ? 0 ? big endian mode. KS32C5000 is fixed to this mode. dram/sdram configurations snds100 has the 72-pin simm module on the board for one bank dram. ks32c50100 can support synchronous dram(sdram). in this case, sdram or dram memory can be selected alternatively using by syscfg register. KS32C5000(a) did not support sdram type. using these device with snds100, jp2 have to be set to select dram. bank select jumper for dram/sdram, jp2/jp1 on snds100 are provided just only for the purpose of each bank test. so, you want to use sdram, you have to enable a sdram bank and remove same dram bank ? s jumper. boot rom code find out the type of memory which is installed on snds100 , and then initialize the memory banks, base/end pointer and the timing of cas/ras after the system power on reset or the reset key pressed and released. if dram banks are found, each bank can be configured as an edo dram mode using the system management block dram bank control register.
ks32c50100/5000a risc microcontroller a bout snds100 board 1- 9 rom and external i/o bank chip select jumpers(j8) snds100 also provides rom and external i/o bank selection jumper for the purpose of each bank test using by sram(u20, u21, u19, u22). ? rs1 ~ r25 : rom/sram/flash bank selection jumpers. ? es0 ~ es3 : external i/o bank selection jumpers. these bank selection jumper(j8) have to be enabled only one bank, if you want to use it. status lcd driver snds100 provide lcd display to indicate snds100 status. external i/o bank 0 is used to control the lcd driver. the lcd driver interface connector pin numbers are described in table 1-4. table 1-4. lcd driver interface pin no. descriptions 1 gnd 2 vcc 3 resolution control 4 a[1] 5 a[0] 6 chip select [14:7] data[7:0] general i/o ports ks32c50100/KS32C5000(a) 's general i/o ports are used for snds100 key interrupt input and led status display. the function of control switch and the status of led can be defined by user software. table 1-5. general i/o configurations on snds100 general i/o port number i/o type descriptions p[7:0] output led display p[11:8] input key input pad (external interrupt input pins). p[17:16] output hdlc data set ready signal output( ndsrb/ ndsra).
about snds100 board ks32c50100/500 0a risc microcontroller 1- 10 ethernet interface ks32c50100/KS32C5000(a) has one 10-/100-mbps ethernet controller. snds100 supports 10-/100-mbps ethernet interface, a phy chip set used in snds100 is able to operate 10-/100-m bps using auto-negotiation and communicate with ks32c50100/KS32C5000(a) using an mii interface. snds100 ethernet connector(rj45) has ethernet adapter side pin configuration which supports communication between the snds100 and the host pc's nic. you can connect snds100 to hub or router direct without twisting cable. both receive and transmit domains must be connected to the digital domain through a ferrite bead or inductor. the value of the inductor is from 0.1uh to 1uh. jumpers(j3-1,j3-2) are located between the mii interface of netmcu mac and phy for another phy chip. user who would like to use any other vendor ? s phy chip can use this jumpers as interface a daughter board. these jumpers should be always enabled for mac evaluation. the pcb power plane and rj45 connector(j1) configurations are shown in figure 1-8. netmcu 10/100 mbps phy xfmrs xfatm2- combo1-2 9901 combo type rj45 connector receive domain transmit domain main digital domain jumper(j3-1,j3-2) figure 1-8. ethernet i/f pcb power plane on snds100 table 1-6. rj45 pin configurations for adapter side pin number descriptions pin number descriptions 1 cmt 5 nc 2 ct_t 6 ct_r 3 tx+ 7 rx+ 4 tx- 8 rx-
ks32c50100/5000a risc microcontroller a bout snds100 board 1- 11 ethernet status led ? led location : d1, d2, d3, d4, d5 ? indicate the line status, operation mode and speed. table 1-7. ethernet status led. led functions descriptions d1 activity line status led. indicate full-duplex operation. d2 rx receive data led. d3 tx transmit data led. d4 li link integrity led. d5 col collision detected. speed activity led. indicate 100mbps operation. hdlc test circuit configurations snds100 board provides hdlc external loop back test jumper(jp5,jp6,jp7). configuring the jumper set, you can test the external loop back between the hdlc channel. also you can select the hdlc oscillator for external hdlc clock input using by jp6. rs232c port b rs232c port a hdlc b hdlc a jp5 jp7 gnd dcda ctsa rtsa dsra dtra rxda txda rxca txca rtsb ctsb dtrb dsrb txdb rxdb dcdb gnd txcb rxcb jp5 jp7 jp5 jp7 jp5 jp7 jp5 jp7 a b a b a b a b (a) (b) (c) (d) (a) hdlc-a channel external loop back test (from channel a to a) (b) hdlc-b channel external loop back test (from channel b to b) (c) hdlc channel a to b external loop back test (from channel a to b or b to a) (d) hdlc channel a to b external test (interface with v.24/rs232) figure 1-9. hdlc jumper setting for external loop back test
about snds100 board ks32c50100/500 0a risc microcontroller 1- 12 hdlc external clock txca rxca txcb rxcb jp6 (a) (b) (c) (a) hdlc external clock used for hdlc channel a tx/rx input clock (b) hdlc external clock used for hdlc channel a tx/rx input clock (c) hdlc external clock used for rx input clock of hdlc channel a and b figure 1-10. hdlc tx/rx clock input configurations serial (hdlc, uart) & jtag interface snds100 board supports the two 9dip sub serial connector for two channel uart(p2a sio-0, p2b sio-1). if you want to get the connector pin configurations, please refer to ? section 2 ? . netmcu device have the two-channel hdlc(high level data link controllers) for serial communication. the snds100 provides serial communication port(hdlc-a p1a, hdlc-b p1b) with v.24/rs-232 interface. snds100 support jtag port. it can be used as circuit emulator(ex, embedded ice) interface for boundary scan test and debugging channel for application. for the details, see the ? section 4. system design ? . snds100 rev. 1.0. board schematics 1. main.sch : snds100 top schematic 2. mcu.sch : netmcu(ks32c50100/5000(a)) device interface 3. system.sch : rev. 1.0 4. system.sch : rev. 1.1 5. dram.sch : dram/sdram schematics 6. ethernet.sch 7. external.sch 8. hdlc.sch : rev. 1.0 9. hdlc.sch : rev. 1.1 10. rom.sch 11. sram.sch 12. uart.sch : rev. 1.0 13. uart.sch : rev. 1.1 14. bill of materials
ks32c50100/5000a risc microcontroller a bout snds100 board 1- 13 bill of materials of snds100 rev1.0 snds100(samsung netmcu development system) revised: saturday, january 16, 1999 main.sch revision: 1.0 kims technology co. #h-305 konggu sangga ilbeongi #636-62, kuro-dong, kuro-gu seoul, korea 152-050 e-mail: kimstek@unitel.co.kr bill of materials march 5,1999 12:22:22 page1 item quantity reference part 1 98 c1, c2, c3, c4, c5, c6, c7, c8, c9, c10, c11, c12, c13, c14, c15, c16, c17, c18, c19, c20, c21, c25, c26, c27, c30, c31, c32, c33, c34, c35, c36, c37, c38, c39, c40, c41, c42, c43, c44, c45, c46, c47, c48, c49, c50, c51, c52, c53, c54, c55, c56, c57, c58, c59, c60, c61, c62, c63, c64, c65, c66, c67, c68, c69, c70, c71, c72, c73, c74, c75, c76, c77, c78, c79, c80, c81, c82, c83, c84, c85, c86, c87, c88, c89, c94, c98, c99, c100, c101, c102, c103, c104, c109, c110, c111, c112, c113, c114 0.1uf 2 1 c22 0.001uf/2kv 3 5 c23, c24, c28, c91, c120 10uf 4 1 c90 10uf/16v 5 1 c92 0.1uf 6 1 c93 820pf 7 1 c95 100uf/6.3v 8 1 c96 100uf/16v 9 1 c97 100uf/10v 10 8 c105, c106, c107, c108, c115, c116, c117, c118 330pf 11 25 d1, d2, d3, d4, d5, d6, d7, d8, d9, d10, d11, d12, d13, d14, d15, d16, d17, d18, d19, d20, d21, d22, d23, d26, d27 led 12 1 d24 1n4148 13 1 d25 1n4004 14 3 jp1, jp2, jp6 header 4x2 15 2 jp5, jp7 header 10x2 16 1 jp8 header 9x2 17 1 jp9 header 3x2 18 1 jp10 header 7x2 19 1 j1 xfatm2-combo-4 20 8 j2, j3, j4, j5, j6, j7, j8, j11 con3
about snds100 board ks32c50100/500 0a risc microcontroller 1- 14 item quantity reference part 21 2 j9, j12 con1 22 1 j10 dc_jack 23 4 j2-1, j2-2, j2-3, j2-4 header 26x2 24 2 j3-1, j3-2 header 11x2 25 9 l1, l2, l3, l4, l5, l6, l7, l9, l11 f.b 26 2 p1a, p1b connector db25 27 1 p2 connector db9x2 28 12 r1, r2, r3, r4, r5, r6, r21, r47, r49, r51, r57, r61 22 29 16 r7, r8, r9, r10, r11, r37, r38, r39, r40, r41, r42, r43, r44, r45, r46, r58 680 30 2 r13, r14 49.9 31 1 r15 22k 1% 32 1 r17 100 33 2 r18, r59 1k 34 3 r19, r34, r35 2k 35 4 r20, r28, r52, r60 10k 36 8 r22, r23, r24, r25, r26, r27, r29, r30 330 37 9 r31, r32, r33, r36, r48, r50, r54, r55, r56 4.7k 38 1 r53 33 39 5 s1, s2, s3, s4, s5 sw pushbotton 40 1 s6 sw_dip4 41 1 s7 sw on/off 42 2 u1, u2 km416s4020b 43 1 u3 dram_simm 44 1 u4 levelone 45 1 u5 osc(25mhz) 46 2 u6, u23 7414 47 1 u7 lcon14 48 1 u8 ks24c641 49 7 u9, u10, u11, u12, u13, u28, u29 max232 50 3 u14, u16, u25 osc 51 1 u15 ks32c50100 52 2 u17, u18 29e010 53 4 u19, u20, u21, u22 ks681000c_55(sop) 54 1 u24 7408 55 1 u26 78r05 56 1 u27 78r33
a a b b c c d d e e 4 4 3 3 2 2 1 1 snds100 board ver1.0 (for netarm : KS32C5000/ks32c50100) external ports - general i/o - control/status - lcd driver - i2c eeprom page4 system - power - reset - clock - jtag port - control switch - status led page9 hdlc - 2 channel serial comm port - dsub 25 pin interface page5 ethernet - ieee802.3 physical ethernet interface - phy - magnetic - rj45 adapter side pin configuration page3 mcu - KS32C5000/ks32c50100 (netarm) - probe header page6 dram - 1 bank dram 72 pin simm . edo dram supported rom - bootrom 2 byte size - configurable byte size - flash rom support page2 page7 sram - 1 bank sram 4 byte size page8 uart - 2 channel serial port - one for consol page10 - 1 bank sdram main.sch 1.0 snds100(s amsung netarm development system) b 1 10 friday, march 05, 1999 samsung elec tronics co., ltd. title size document num ber rev date: sheet of rom rom.sch noe xdata[0. .15] addr[ 0..18] nwbe[0..1] nrcs0 sram sra m.sch nwbe[0..3] nrcs[1..5] noe addr[ 0..16] xdata[0. .31] necs[0..3] system sys tem.sch tdi tms tck tdo nreset little clksel cpump[0..2] b0size[0..1] tmod0 clkoen ntrst uclk(tmode1) uart uart. sch uatxd0 uatxd1 uarxd0 uarxd1 nuadsr0 nuadsr1 nuadtr0 nuadtr1 etherne t ethern et.sch nreset mdio mdc txen txer rxdv rxclk rxer txclk col crs txd[0..3] rxd[0..3] hdlc hdlc. sch txda txcb rxda rxcb txca rxca ndtra ndsra nrtsa nctsa ndcda rxdb txdb ndsrb ndtrb ndcdb nrtsb nctsb dram dram. sch ndwe addr[ 0..13] xdata[0. .31] nras[0..3] ncas[0..3] sdclk(mclk o) nwbe[0..3] mcu m cu.sch clksel nreset tck tms tdi ntrst little rxda tdo ndwe noe mdc txda uatxd0 txdb uatxd1 xdata[0..31] b0 size[0..1] rxd[0..3] cpump[ 0..2] addr[0..21] nras[0..3] necs[0..3] nrcs[0..5] nwbe[0..3] ncas[0..3] txd[0..3] col crs txclk rxclk rxdv rxer txen txer mdio uarxd0 rxdb uarxd1 p[0..7] scl sda tmod0 sdclk(mclko) eintr[0..3] txca rxca ndtra ndsra nrtsa nctsa ndcda txcb rxcb ndsrb ndtrb nctsb nrtsb ndcdb clkoen nuadsr0 nuadsr1 nuadtr0 nuadtr1 u clk(tmode1) ex ternal e xternal.sch scl sda p[0..7] ad dr[0..1] xdat a[0..7] eint r[0..3] necs0 cpump[ 0..2] b0 size[0..1] txd[0..3] rxd[0..3] ncas[0..3] nras[0..3] p[0..7] necs[0..3] eint r[0..3] xdata[0. .31] nrcs[0..5] addr[ 0..21] nwbe[0..3] tdi ntrst tdo uatxd0 uatxd1 uarxd1 tck uarxd0 u clk(tmode1) tmod0 clksel tms clkoen rx_err tx_ en/txen_10m c ol/col_10m tx_clk/t xclk_10m rx_clk/r xclk_10m crs/cr s_10m tx_err/pcom p_10m rx_dv/link_1 0m mdio mdc little(sel_10m ) nreset nuadtr0 nuadtr1 nuadsr1 nuadsr0 ndsrb ndcda nctsa txda nrtsb rxca rxda txdb rxdb txcb rxcb nrtsa ndcdb ndtra nctsb ndtrb ndsra txca sdclk(mclk o) ndwe noe scl sda nrcs0
a a b b c c d d e e 4 4 3 3 2 2 1 1 ne tarm ks32c501 00 main clock osc 10mhz : dpll clock 50mhz : direct clock gnd vss mcu.sch 1.0 snds100 (samsung neta rm development system) c 6 10 saturday, january 1 6, 1999 samsung electro nics co.ltd,. title size documen t number rev date: sheet of ncas[0..3] nrcs[0..5] txd[0..3] rxd[0..3] nras[0..3] addr[0..21] nrcs 0 mcl k ndw e eintr3 xdata30 ebreq addr18 addr7 nsyncb ncas3 txdb necs1 nuadtr1 txcb nctsa uatxd1 ndsrb p4 p2 xdata13 xdata6 txer txd2 addr5 ncas0 nrcs3 b0size1 col rxd2 ndsra tdo tm s rxd2 nwbe0 nrcs5 clksel noe tdo txda ndtra nuadtr1 ncas1 p3 xdata22 txen txd3 addr14 txcb b0size0 uatxd1 mdio txca nuadtr0 p1 xdata28 xdata21 mdio txd1 ebreq nras1 nrcs2 txca rxca txd3 rxd3 nuadsr1 eintr2 addr20 addr16 rxdv ncas2 rxda nuadsr1 txd1 ndsrb ndsra nras1 nrcs 5 nrcs 3 xdata27 xdata11 little xdata0 addr8 rxd3 nwbe1 ndtra txd2 rxclk rxd1 edmaa1 eintr1 xdata3 addr19 nwbe3 ndwe nrcs4 cpump0 rxcb nrcs 2 edmaa0 eintr0 xdata10 xdata2 addr13 addr12 addr10 rxer addr0 nras2 txda cpump1 rxd0 nrese t sda p6 tc k xdata20 xdata16 txd0 rxclk nctsb nras0 clkoen necs3 uarxd1 sdclk(mcl ko) noe edmar1 p7 p0 addr15 addr2 newait nrtsa tck txd0 rxer rxdv nrtsa clksel xdata26 xdata19 xdata15 xdata9 mdc addr21 addr17 col addr4 nwbe2 nras3 sdclk (mclko) nrcs0 necs2 tdi txen ndcdb ncas3 ncas2 ncas0 nras3 ndwe scl xdata31 xdata12 rxdb ndtrb nctsa cpump2 rxda xdata24 xdata8 xdata1 addr11 addr9 addr6 ebgnt ndcda tms mdc nctsb rxdb nras2 nras0 nrcs 4 p5 xdata25 xdata18 rxd0 ndcdb nrcs1 nsynca txdb nuadsr0 uarxd0 edmar0 xdata23 xdata7 xdata5 ebgnt txclk addr1 crs rxcb mclk little crs ndtrb ndcda nrcs1 uatxd0 tdi xdata29 xdata17 xdata14 xdata4 addr3 rxd1 ncas1 nrtsb necs0 txclk txer nrtsb rxca addr15 addr9 addr5 addr16 addr11 addr6 addr13 addr2 addr3 addr1 addr17 addr10 addr18 addr19 addr7 addr0 addr8 addr4 addr14 addr12 addr21 addr20 xdata15 xdata1 xdata9 xdata6 xdata4 xdata7 edmaa[0..1] xdata13 xdata10 xdata5 xdata12 xdata3 xdata11 xdata0 eintr[0..3] xdata8 xdata2 xdata16 p[0..7] xdata[0..31] edmar[0..1] xdata14 xdata26 eintr2 xdata18 sda xdata2 1 edma r0 uarx d1 ein tr3 xdata3 1 xdata2 7 p6 xdata1 7 xdata2 8 p7 scl edmaa 0 p3 xdata2 0 xdata2 4 uatx d0 xdata3 0 ein tr1 p2 edmaa 1 p5 uarx d0 nuad tr0 xdata1 9 xdata2 9 xdata2 3 edma r1 ein tr0 xdata2 2 xdata2 5 p4 p0 nwbe2 nwbe1 nwbe0 nwbe3 b0size 0 b0size1 clkoen b0size[0..1] necs[0..3] necs0 necs3 newait necs1 necs2 tmod0 uclk( tmode1) nwbe[0..3] cpum p1 cpum p2 cpump[0..2] cpum p0 p1 ndsra ndsrb nuads r0 ntrst ntrst nreset tmod0 uclk( tmode1) vdd_cpu vdd_cpu vdd_cpu vdd_cpu vdd_cpu vdd_cpu vddd vcc vddd c59 0.1uf c60 0.1uf c61 0.1uf c62 0.1uf c63 0.1uf c64 0.1uf c65 0.1uf c66 0.1uf c67 0.1uf c68 0.1uf c69 0.1uf c70 0.1uf c71 0.1uf c72 0.1uf c73 0.1uf c74 0.1uf c79 0.1uf c77 0.1uf c75 0.1uf c76 0.1uf c78 0.1uf c80 0.1uf r48 4.7k r50 4.7k r49 22 l7 f.b. u16 osc nc 1 gnd 4 vcc 14 out 11 gnd1 7 out1 8 u15 ks32c50100 vdd53 53 vss54 54 filter(cpump0) 55 vdda(cpump1) 56 vssa(cpump2) 57 tck 58 tms 59 tdi 60 tdo 61 ntrst 62 tmode0 63 uclk(tmode1) 64 vdd65 65 vss66 66 necs0 67 necs1 68 necs2 69 necs3 70 newait 71 noe 72 b0size0 73 b0size1 74 nrcs0 75 clkoen 76 mclko/sdclk 77 vdd78 78 vss79 79 mclk 80 vss81 81 nreset 82 clksel 83 nrcs1 84 nrcs2 85 nrcs3 86 nrcs4 87 nrcs5 88 nras0/nsdcs0 89 nras1/nsdcs1 90 nras2/nsdcs2 91 vdd92 92 vss93 93 nras3/nsdcs3 94 ncas0/nsdras 95 ncas1/nsdcas 96 ncas2/cke 97 ncas3 98 ndwe 99 nwbe0/dqm0 100 nwbe1/dqm1 101 nwbe2/dqm2 102 vdd103 103 vss104 104 vdd1 1 vss2 2 nuadtr1 3 uatxd1 4 nuadsr1 5 ndtra 6 rxda 7 nrtsa 8 txda 9 nctsa 10 vdd11 11 vss12 12 ndcda 13 rxca 14 nsynca 15 txca 16 ndtrb 17 rxdb 18 nrtsb 19 txdb 20 vdd21 21 vss22 22 nctsb 23 ndcdb 24 rxcb 25 nsyncb 26 txcb 27 c rs/crs_10m 28 rx_dv/l ink_10m 29 rxd 0/rxd_10m 30 vdd31 31 vss32 32 rxd1 33 rxd2 34 rxd3 35 rx_err 36 rx_clk/rxc lk_10 37 col/col_10m 38 txd0/t xd_10m 39 txd1/l oop_10m 40 vdd41 41 vss42 42 txd2 43 txd3 44 tx_err/pcomp _10 45 tx_clk/txclk _10 46 tx_ent/en _10m 47 mdio 48 little(nc) 49 mdc 50 vdd51 51 vss52 52 vdd105 105 vss106 106 nwbe3/dqm3 107 extmreq 108 extmack 109 addr0 110 addr1 111 addr2 112 addr3 113 addr4 114 addr5 115 addr6 116 addr7 117 vdd118 118 vss119 119 addr8 120 addr9 121 addr10/ap 122 addr11 123 addr12 124 addr13 125 addr14 126 addr15 127 addr16 128 addr17 129 vdd130 130 vss131 131 addr18 132 addr19 133 addr20 134 addr21 135 xdata0 136 xdata1 137 xdata2 138 xdata3 139 xdata4 140 xdata5 141 vdd142 142 vss143 143 xdata6 144 xdata7 145 xdata8 146 xdata9 147 xdata10 148 xdata11 149 xdata12 150 xdata13 151 xdata14 152 xdata15 153 xdata16 154 vdd155 155 vss156 156 vdd157 157 vss158 158 xdata1 7 159 xdata1 8 160 xdata19 161 xdata2 0 162 xdata2 1 163 xdata22 164 xdata2 3 165 xdata2 4 166 vdd167 167 vss168 168 xdata2 5 169 xdata2 6 170 xdata27 171 xdata2 8 172 xdata2 9 173 xdata30 174 xdata3 1 175 p0 176 vdd177 177 vss178 178 p1 179 p2 180 p3 181 p4 182 p5 183 p6 184 p7 185 p8/ei ntr0 186 vdd187 187 vss188 188 p9/ei ntr1 189 p10/ei ntr2 190 p11/eintr3 191 p12/edm ar0 192 p13/edm ar1 193 p14/edmaa0 194 p15/edma a1 195 p16/ti mer0 196 vdd197 197 vss198 198 p17/ti mer1 199 scl 200 sda 201 uarx d0 202 nuad tr0 203 uatxd0 204 nuads r0 205 uarx d1 206 vdd207 207 vss208 208 j2-3 header26x2 1 1 3 3 5 5 7 7 2 2 4 4 6 6 8 8 9 9 10 10 11 11 12 12 13 13 14 14 15 15 16 16 18 18 19 19 20 20 21 21 22 22 23 23 24 24 25 25 26 26 27 27 28 28 29 29 30 30 31 31 32 32 33 33 34 34 35 35 36 36 37 37 38 38 39 39 40 40 41 41 42 42 43 43 44 44 45 45 46 46 47 47 48 48 49 49 50 50 51 51 52 52 17 17 j2-4 header26x2 1 1 3 3 5 5 7 7 2 2 4 4 6 6 8 8 9 9 10 10 11 11 12 12 13 13 14 14 15 15 16 16 18 18 19 19 20 20 21 21 22 22 23 23 24 24 25 25 26 26 27 27 28 28 29 29 30 30 31 31 32 32 33 33 34 34 35 35 36 36 37 37 38 38 39 39 40 40 41 41 42 42 43 43 44 44 45 45 46 46 47 47 48 48 49 49 50 50 51 51 52 52 17 17 j2-2 header26x2 1 1 3 3 5 5 7 7 2 2 4 4 6 6 8 8 9 9 10 10 11 11 12 12 13 13 14 14 15 15 16 16 18 18 19 19 20 20 21 21 22 22 23 23 24 24 25 25 26 26 27 27 28 28 29 29 30 30 31 31 32 32 33 33 34 34 35 35 36 36 37 37 38 38 39 39 40 40 41 41 42 42 43 43 44 44 45 45 46 46 47 47 48 48 49 49 50 50 51 51 52 52 17 17 j2-1 header26x2 1 1 3 3 5 5 7 7 2 2 4 4 6 6 8 8 9 9 10 10 11 11 12 12 13 13 14 14 15 15 16 16 18 18 19 19 20 20 21 21 22 22 23 23 24 24 25 25 26 26 27 27 28 28 29 29 30 30 31 31 32 32 33 33 34 34 35 35 36 36 37 37 38 38 39 39 40 40 41 41 42 42 43 43 44 44 45 45 46 46 47 47 48 48 49 49 50 50 51 51 52 52 17 17 c58 0.1uf clksel nreset uatxd0 nrtsa scl uarxd0 ncas[0..3] ndwe edmar[0..1] txca rxca txdb rxdb nctsa ndcdb rxclk noe p[0..7] rxd[0..3] crs txen nrcs[0..5] uatxd1 tdo necs[0..3] edmaa[0..1] sda tdi tck eintr[0..3] uarxd1 little rxda nras[0..3] ndtrb txda xdata[0..31] ndcda mdio nctsb nrtsb rxdv txcb rxcb txclk col sdclk (mclko) b0size[0..1] tms mdc ndtra nwbe[0..3] ntrst tmod0 uclk( tmode1) rxer txer addr[0..21] cpump[0..2] txd[0..3] clkoen nsynca nsyncb newait ndsrb ndsra nuadtr0 nuadsr0 nuadtr1 nuadsr1 ebgnt ebreq
a a b b c c d d e e 4 4 3 3 2 2 1 1 reset logic po wer connector distributed power used vddd : m ain power for test board vdd33 : mcu, sdram only power power led jtag/e-ice connector ntrst heat sink (ceramic) b0size[0..1] 00: reserved (default) 01: byte 10: half w orld(used) 11: word uart clock osc jp 1-2 3-4 5-6 ------- ------------------------------- KS32C5000 : open open open ks32c 50100 : short short short sw_dip4(3-6) ------ -------------------------------- on : little off : big => pull down internally 1- 2(vcc) : chip test mode 2 -3(gnd) : normal mode for both KS32C5000 and ks32c50100 ( maybe always u se normal mode) fo r KS32C5000 for ks3 2c50100 1-2(vcc) : mclk/2 2-3(gnd) : mclk 1-2 (vcc) : external master clock 2-3(gnd) : pll output cloc k for both KS32C5000 and ks32c50100 1-2(vcc) : mclk o output enable 2-3(gnd) : mclko o utput disable when use s dram mclko should be enabled over 5v gnd 9v power heat sink KS32C5000 ks32c50100 cpump2 vssa cpump1 vd da cp ump0 filter ks32c500 0 : 2-3(gnd) ks32c501 00 : 1-2 (clk) fo r KS32C5000 u27 (regurator) will be removed gnd vss KS32C5000 : j5 j6 j7 j8 1-2 1-2 1-2 1-2 ks32c50100 : j5 j6 j7 j8 2-3 2-3 2-3 2-3 -------------------- -------------------- c pu_gnd sys tem.sch 1.0 snds100 ( samsung netarm development system) b 9 10 friday, march 05, 1999 samsung elect ronics co.ltd,. title size document num ber rev date: sheet of nreset tdi tck tdo tms little b0size1 b0size0 b0 size[0..1] tmod0 clksel clkoen cpump1 cpump2 cpump0 ntrst uc lk(tmode1) vdd33 v dd_cpu vdd33 v dd_cpu v dd_cpu vddd vddd vddd v dd_cpu vdd33 vddd vddd vddd vddd vcc vddd v dd_cpu vddd vdd33 r52 10k d24 1n4148 c90 10uf/16v + c97 100uf/10v + r58 680 d26 led r53 33 s7 sw o n/off c95 1 00uf/6.3v + s6 sw_dip4 1 2 3 4 8 7 6 5 r55 4.7k c93 820pf c92 0.01uf c91 10uf + r56 4.7k j2 con3 1 2 3 j3 con3 1 2 3 s5 sw pushb utton c98 0.1uf c99 0.1uf r57 22 l9 f.b. j4 con3 1 2 3 jp9 header 3x 2 1 2 3 4 5 6 r54 4.7k j9 con1 1 j12 con1 1 u25 osc nc 1 gnd 4 vcc 14 out 11 gnd1 7 out1 8 c89 0.1uf c88 0.1uf c87 0.1uf j11 con3 1 2 3 u6f 7414 13 12 u23a 7414 1 2 u24a 7408 1 2 3 c94 0.1uf d25 1n4004 c96 100uf/16v + j5 con3 1 2 3 j6 con3 1 2 3 j7 con3 1 2 3 j8 con3 1 2 3 jp10 header 7x 2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 r60 10k l11 f.b. j10 dc_jack 1 2 3 u26 78r05 vin 1 vout 2 gnd 3 vdis 4 u27 78r33 vin 1 vout 2 gnd 3 vdis 4 nreset tdi tdo little b0 size[0..1] tmod0 clksel tck tms uc lk(tmode1) clkoen cpump[0 ..2] ntrst
a a b b c c d d e e 4 4 3 3 2 2 1 1 reset logic power connector distributed power used vddd : main power for test board vdd33 : mcu, sdram only power power led jtag /e-ice connector heat sink (ceramic) b0size[0..1] 00: reserved(default) 01: byte 10: half world(used) 11: word u art clock osc jp 1-2 3-4 5-6 -- ------------------------------------ KS32C5000 : open open open ks32c50100 : short short short sw_dip4(3-6) -- ------------------------------------ on : little off : big => pull down internally 1-2(vcc) : chip test mode 2-3(gnd) : normal mo de for both KS32C5000 and ks32c50100 ( maybe always use normal mode) for ks32c500 0 for ks32c5010 0 1-2(vcc) : mclk/2 2-3(gnd) : mclk 1-2(vcc) : external master clock 2-3(gnd) : pll output clock for both KS32C5000 and ks32c50100 1-2(vcc) : mclko output enable 2-3(gnd) : mclko output disable when use sdram mclko should be enable d over 5v gnd 9v power heat sink KS32C5000 ks32c50100 cpump2 vssa cpump1 vdda cpump0 filter KS32C5000 : 2-3(gnd) ks32c50100 : 1-2 (clk) for ks32c500 0 u27 (regurator) will be removed gnd vss KS32C5000 : j5 j6 j7 j8 1-2 1-2 1-2 1-2 ks32c50100 : j5 j6 j7 j8 2-3 2-3 2-3 2-3 ---------------------------------------- cpu_gnd system.sch 1.1 snds100 (samsu ng netarm development system) b 9 10 thursday, june 10, 1999 samsung electronics co.ltd,. title size document number rev date: sheet of nreset tdi tck tdo tms litt le b0size1 b0size0 b0size[0..1] tmod0 clksel clkoen cpump1 cpump2 cpump0 ntrst uclk(tmode1) vdd33 vdd_cpu vdd33 vdd_cpu vdd_cpu vddd vddd vddd vdd_cpu vdd33 vddd vddd vddd vddd vcc vddd vdd_cpu vddd vdd33 r52 10k d24 1n4148 c90 10uf/16v + c97 100uf/10v + r58 680 d26 led r53 0 s7 sw on/off c95 100uf/6.3v + s6 sw_dip4 1 2 3 4 8 7 6 5 r55 4.7k c93 820pf c92 0.01uf c91 10uf + r56 4.7k j2 con3 1 2 3 j3 con3 1 2 3 s5 sw pushbutton c98 0.1uf c99 0.1uf r57 22 l9 f.b. j4 con3 1 2 3 jp9 header 3x2 1 2 3 4 5 6 r54 4.7k j9 con1 1 j12 con1 1 u25 osc nc 1 gnd 4 vcc 14 out 11 gnd1 7 out1 8 c89 0.1uf c88 0.1uf c87 0.1uf j11 con3 1 2 3 u6f 7414 13 12 u23a 7414 1 2 u24a 7408 1 2 3 c94 0.1uf d25 1n4004 c96 100uf/16v + j5 con3 1 2 3 j6 con3 1 2 3 j7 con3 1 2 3 j8 con3 1 2 3 jp10 header 7x2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 r60 10k l11 f.b. j10 dc_jack 1 2 3 u26 78r05 vin 1 vout 2 gnd 3 vdis 4 u27 78r33 vin 1 vout 2 gnd 3 vdis 4 j13 con5 1 2 nreset tdi tdo littl e b0size[0..1] tmod0 clksel tck tms uclk(tmode1) clkoen cpump[0..2] ntrst
a a b b c c d d e e 4 4 3 3 2 2 1 1 gnd vss dram. sch 1.0 snds100 ( samsung netarm development system) b 2 10 th ursday, january 21, 1999 samsung elect ronics co.ltd,. title size document num ber rev date: sheet of nras3 nras2 addr0 addr1 addr2 addr3 addr4 addr5 addr6 addr7 addr8 addr9 addr10 addr11 t(ncas3) cke(ncas2 ) n sdcas(ncas1) nsdras(ncas0 ) nsdcas(ncas1 ) n sdras(ncas0) xdata24 xdata28 xdata1 xdata16 xdata29 xdata19 xdata30 xdata6 xdata5 xdata12 xdata18 xdata3 xdata17 xdata14 xdata25 xdata13 xdata31 xdata9 xdata27 xdata15 xdata21 xdata0 xdata2 xdata23 xdata20 xdata26 xdata22 xdata4 xdata8 xdata10 xdata11 xdata7 nwbe[0..3] ndwe addr4 addr3 ncas[0..3] addr6 addr0 xdata4 xdata3 xdata7 xdata6 addr9 xdata1 addr10 ncas1 xdata2 addr11 nwbe0 xdata5 addr5 addr2 addr1 ncas0 xdata0 addr8 addr7 nsdcs addr[ 0..13] xdata[0. .31] c ke(ncas2) addr12 xdata8 xdata9 xdata10 xdata11 xdata12 xdata13 xdata14 xdata15 n sdcas(ncas1) n sdras(ncas0) cke(ncas2 ) ncas2 nwbe1 addr13 addr4 addr3 addr6 addr0 addr9 addr10 addr11 nwbe2 addr5 addr2 addr1 xdata16 addr8 addr7 nsdcs addr12 nwbe3 addr13 nsdcs nras[0..3] nras0 xdata17 xdata18 xdata19 xdata20 xdata21 xdata22 xdata23 xdata24 xdata25 xdata26 xdata27 xdata28 xdata29 xdata30 xdata31 ncas3 t(ncas3) nras nras nras1 c ke(ncas2) n sdcas(ncas1) n sdras(ncas0) vddd vdd33 vdd33 vdd33 vdd33 vddd vcc vddd r3 22 r2 22 u3 dram_sim m a0 12 a1 13 a2 14 a3 15 a4 16 a5 17 a6 18 a7 28 a8 31 ras0 44 cas0 40 w 47 vdd2 30 vdd1 10 gnd1 1 gnd2 39 a9 32 a10 19 a11 29 dq0 2 dq1 4 dq2 6 dq3 8 dq4 20 dq5 22 dq6 24 dq7 26 dq9 49 dq10 51 dq11 53 dq12 55 dq13 57 dq14 61 dq15 63 dq16 65 dq18 3 dq19 5 dq20 7 dq21 9 dq22 21 dq23 23 dq24 25 dq25 27 dq27 50 dq28 52 dq29 54 dq30 56 dq31 58 dq32 60 dq33 62 dq34 64 vdd3 59 gnd3 72 ras2 34 cas1 43 cas2 41 cas3 42 pd1 67 pd2 68 pd3 69 pd4 70 nc 11 nc 33 nc 35 nc 36 nc 37 nc 38 nc 45 nc 46 nc 48 nc 66 nc 71 r5 22 u1 km416s402 0b a0 23 a1 24 a2 25 a3 26 a4 29 a5 30 a6 31 a7 32 a8 33 ras 18 cas 17 we 16 vddq1 3 vdd1 1 vssq1 6 vss1 28 a9 34 a10/ap 22 a11 35 dq0 2 dq1 4 dq2 5 dq3 7 dq4 8 dq5 10 dq6 11 dq7 13 vss2 41 cs 19 ldqm 15 ba 20 udqm 39 clk 38 cke 37 dq8 42 dq9 44 nc/fru 40 nc 36 dq15 53 dq14 51 dq13 50 dq12 48 dq11 47 dq10 45 vdd3 27 vddq2 9 vdd2 14 vddq3 43 vddq4 49 a12 21 vssq2 12 vssq3 46 vssq4 52 vss3 54 u2 km416s402 0b a0 23 a1 24 a2 25 a3 26 a4 29 a5 30 a6 31 a7 32 a8 33 ras 18 cas 17 we 16 vddq1 3 vdd1 1 vssq1 6 vss1 28 a9 34 a10/ap 22 a11 35 dq0 2 dq1 4 dq2 5 dq3 7 dq4 8 dq5 10 dq6 11 dq7 13 vss2 41 cs 19 ldqm 15 ba 20 udqm 39 clk 38 cke 37 dq8 42 dq9 44 nc/fru 40 nc 36 dq15 53 dq14 51 dq13 50 dq12 48 dq11 47 dq10 45 vdd3 27 vddq2 9 vdd2 14 vddq3 43 vddq4 49 a12 21 vssq2 12 vssq3 46 vssq4 52 vss3 54 r1 22 jp1 header 4x 2 1 2 3 4 5 6 7 8 r6 22 c1 0.1uf c2 0.1uf c3 0.1uf c4 0.1uf c5 0.1uf c6 0.1uf c7 0.1uf c8 0.1uf c9 0.1uf c10 0.1uf c11 0.1uf c12 0.1uf c13 0.1uf c14 0.1uf c16 0.1uf c15 0.1uf c17 0.1uf jp2 header 4x 2 1 2 3 4 5 6 7 8 r4 22 r61 22 r51 22 nras[0..3] ncas[0..3] nwbe[0..3] xdata[0. .31] addr[ 0..13] sdclk(mclk o) ndwe
a a b b c c d d e e 4 4 3 3 2 2 1 1 rj45 for adaptor leds : 100mbps ledr : receiver ledt : transmitter ledl : 100mbps(idle) 10mbps(link) ledc : collision gnd vss leds ledc ledl ledt ledr phy clock osc 1% 1% 1% ethern et.sch 1.0 snds100 ( samsung netarm development system) b 3 10 saturday, january 23, 199 9 samsung elect ronics co.ltd,. title size document num ber rev date: sheet of phy_clk gndt vcct gndt mdio nreset mdc crs col rxer rxclk rxdv rxd3 rxd2 rxd1 rxd0 txer txclk txen txd3 txd2 txd1 txd0 gndr gndt phy_clk vccr gndr vcct gndt vddd vddd vddd vddd vddd vcc vddd vddd vddd d5 led d4 led d3 led d2 led d1 led r7 680 r8 680 c18 0.1uf c19 0.1uf r17 100 c26 0.1uf c25 0.1uf l1 f.b. l2 f.b. r18 1k r19 2k c22 0.001 uf/2kv j1 xfatm 2-combo-4 cmt 1 ct_t 2 tx+ 3 tx- 4 nc 5 ct_r 6 rx+ 7 rx- 8 c21 0.1uf c27 0.1uf r9 680 r10 680 r11 680 r21 22 l5 f.b. u5 osc(25mh z) nc 1 vdd 8 gnd 4 out 5 c31 0.1uf j3-1 hea der 11x2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 j3-2 hea der 11x2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 r59 1k c120 10uf + d27 led r13 49.9 r14 49.9 r15 22k 1% c30 0.1uf l3 f.b. l4 f.b. c28 10uf + c23 10uf + c24 10uf + c20 0.1uf r20 10k u4 levelone col 64 txclk 57 txd3 62 txd2 61 txd1 60 txd0 59 txen 58 txer 56 crs 1 rxclk 54 rxd3 47 rxd2 48 rxd1 49 rxd0 50 rxdv 51 rxer 55 mdc 45 mdio 44 nreset 16 leds 38 ledc 39 ledl 40 ledt 41 ledr 42 xi 12 x0 11 pwrdwn 34 vddd 9 vddo 53 mdint 2 gndd 43 gndo 52 test 10 mf0 8 mf1 7 mf2 6 mf3 5 mf4 4 fibp 27 fibn 28 fibop 17 fibon 18 rbias 25 tref 20 tpop 21 tpon 23 trip 29 trin 30 vcct 19 gndt 22 vcca 24 gnda 26 vccr 37 gndr 31 txd[0..3] rxd[0..3] rxclk col txen txer mdio rxdv rxer crs txclk nreset mdc
a a b b c c d d e e 4 4 3 3 2 2 1 1 l cd driver iic eeprom gnd vss e xternal.sch 1.0 snds100 ( samsung netarm development system) b 4 10 saturday, january 16, 199 9 samsung elect ronics co.ltd,. title size document num ber rev date: sheet of lcda1 lcda0 lcda1 lcda0 xdata0 xdata1 xdata2 xdata3 xdata4 xdata5 xdata6 xdata7 scl sda eintr0 eintr3 p[0..7] p4 p7 p5 eintr2 p6 p3 p0 eintr1 eint r[0..3] p2 p1 addr1 addr0 necs0 xdat a[0..7] vddd vddd vddd vddd vcc vddd vddd r22 330 r28 10k 1 3 2 r34 2k r35 2k d9 led d8 led d7 led d6 led r36 4.7k s4 sw pushb utton r31 4.7k d13 led d12 led d11 led s1 sw pushb utton s3 sw pushb utton s2 sw pushb utton r32 4.7k d10 led u8 ks24c641 nc1 1 nc2 2 nc3 3 vss 4 vcc 8 wp 7 scl 6 sda 5 r33 4.7k 1 2 u7 lcon14 1 2 3 4 5 6 7 8 9 10 11 12 13 14 u6e 7414 11 10 u6a 7414 1 2 u6b 7414 3 4 u6c 7414 5 6 u6d 7414 9 8 r23 330 r24 330 r25 330 r26 330 r27 330 r29 330 r30 330 c114 0.1uf p[0..7] sda eint r[0..3] scl addr1 addr0 necs0 xda ta[0..7]
a a b b c c d d e e 4 4 3 3 2 2 1 1 hdlc serial communicat ion port #a, #b gnd gnd gnd gnd gnd hdlc clock os c rs232c ndtrb ndsrb nrtsb nctsb txca rxca txda rxda ndtra ndsra nrtsa nctsa txca rxca txda rxda ndtra ndsra nrtsa nctsa txcb rxcb txdb rxdb ndtrb ndsrb nrtsb nctsb txcb txdb rxcb rxdb ndtrb nrtsb ndsrb nctsb txca txda rxca rxda ndtra nrtsa ndsra nctsa (dsra : from p16) (dsrb : from p17) dte side(ma il) gnd vss ndcda ndcdb change rxca, txda pin change ndsra, nrtsa pin change rxcb, txdb pin change ndsrb, nrtsb pin hdlc. sch 1.0 snds100(s amsung netarm development system) b 5 10 saturday, january 23, 199 9 samsung elec tronics co., ltd. title size document num ber rev date: sheet of ndtra nctsa ndcda rxca nrtsa rxda txda txca ndsra ndsrb txcb txdb rxdb nrtsb rxcb ndcdb nctsb ndtrb h dlcclk hdlcclk ndtrb ndsrb nrtsb nctsb ndcdb ndtra ndsra nrtsa nctsa ndcda vddd vddd vddd vddd vddd vddd vddd vddd vddd vddd vddd vcc vddd vddd vddd jp5 head er 10x2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 jp6 header 4x 2 1 2 3 4 5 6 7 8 jp7 head er 10x2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 c39 0.1uf + c47 0.1uf + c51 0.1uf + c44 0.1uf + c42 0.1uf + r47 22 c41 0.1uf c46 0.1uf c57 0.1uf c56 0.1uf c54 0.1uf + c49 0.1uf + u14 osc nc 1 gnd 4 vcc 14 out 11 gnd1 7 out1 8 d14 led 1 2 d15 led 1 2 d16 led 1 2 d17 led 1 2 d18 led 1 2 r37 680 1 2 d21 led 1 2 d22 led 1 2 d23 led 1 2 d20 led 1 2 d19 led 1 2 r38 680 1 2 r39 680 1 2 r40 680 1 2 r41 680 1 2 r42 680 1 2 r43 680 1 2 r44 680 1 2 r45 680 1 2 r46 680 1 2 c53 0.1uf p1a connector db25 13 25 12 24 11 23 10 22 9 21 8 20 7 19 6 18 5 17 4 16 3 15 2 14 1 c48 0.1uf + c43 0.1uf + c45 0.1uf + c34 0.1uf + c33 0.1uf + c50 0.1uf + l6 f.b. c35 0.1uf + c52 0.1uf + c40 0.1uf + c32 0.1uf + u9 max232 c1+ 1 c1- 3 c2+ 4 c2- 5 t1o 14 r1i 13 t2o 7 r2i 8 vcc 16 v+ 2 v- 6 gnd 15 t1i 11 r1o 12 t2i 10 r2o 9 c36 0.1uf u10 max232 c1+ 1 c1- 3 c2+ 4 c2- 5 t1o 14 r1i 13 t2o 7 r2i 8 vcc 16 v+ 2 v- 6 gnd 15 t1i 11 r1o 12 t2i 10 r2o 9 c37 0.1uf + c38 0.1uf + u12 max232 c1+ 1 c1- 3 c2+ 4 c2- 5 t1o 14 r1i 13 t2o 7 r2i 8 vcc 16 v+ 2 v- 6 gnd 15 t1i 11 r1o 12 t2i 10 r2o 9 c55 0.1uf + u11 max232 c1+ 1 c1- 3 c2+ 4 c2- 5 t1o 14 r1i 13 t2o 7 r2i 8 vcc 16 v+ 2 v- 6 gnd 15 t1i 11 r1o 12 t2i 10 r2o 9 p1b connector db25 13 25 12 24 11 23 10 22 9 21 8 20 7 19 6 18 5 17 4 16 3 15 2 14 1 u13 max232 c1+ 1 c1- 3 c2+ 4 c2- 5 t1o 14 r1i 13 t2o 7 r2i 8 vcc 16 v+ 2 v- 6 gnd 15 t1i 11 r1o 12 t2i 10 r2o 9 rxda txda nrtsa rxca nctsa ndtra ndcda txca txcb ndcdb ndtrb nctsb txdb rxcb nrtsb rxdb ndsra ndsrb
a a b b c c d d e e 4 4 3 3 2 2 1 1 hdlc serial communicat ion port #a, #b gnd gnd gnd gnd gnd hdlc clock os c rs232c ndtrb ndsrb nrtsb nctsb txca rxca txda rxda ndtra ndsra nrtsa nctsa txca rxca txda rxda ndtra ndsra nrtsa nctsa txcb rxcb txdb rxdb ndtrb ndsrb nrtsb nctsb txcb txdb rxcb rxdb ndtrb nrtsb ndsrb nctsb txca txda rxca rxda ndtra nrtsa ndsra nctsa (dsra : from p16) (dsrb : from p17) dte side(ma il) gnd vss ndcda ndcdb change rxca, txda pin change ndsra, nrtsa pin change rxcb, txdb pin change ndsrb, nrtsb pin hdlc. sch 1.1 snds100(s amsung netarm development system) b 5 10 friday, ma y 14, 1999 samsung elec tronics co., ltd. title size document num ber rev date: sheet of ndtra nctsa ndcda rxca nrtsa rxda txda txca ndsra ndsrb txcb txdb rxdb nrtsb rxcb ndcdb nctsb ndtrb h dlcclk hdlcclk ndtrb ndsrb nrtsb nctsb ndcdb ndtra ndsra nrtsa nctsa ndcda vddd vddd vddd vddd vddd vddd vddd vddd vddd vddd vddd vcc vddd vddd vddd jp5 head er 10x2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 jp6 header 4x 2 1 2 3 4 5 6 7 8 jp7 head er 10x2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 c39 0.1uf + c47 0.1uf + c51 0.1uf + c44 0.1uf + c42 0.1uf + r47 22 c41 0.1uf c46 0.1uf c57 0.1uf c56 0.1uf c54 0.1uf + c49 0.1uf + u14 osc nc 1 gnd 4 vcc 14 out 11 gnd1 7 out1 8 d14 led 1 2 d15 led 1 2 d16 led 1 2 d17 led 1 2 d18 led 1 2 r37 680 1 2 d21 led 1 2 d22 led 1 2 d23 led 1 2 d20 led 1 2 d19 led 1 2 r38 680 1 2 r39 680 1 2 r40 680 1 2 r41 680 1 2 r42 680 1 2 r43 680 1 2 r44 680 1 2 r45 680 1 2 r46 680 1 2 c53 0.1uf p1a connector db25 13 25 12 24 11 23 10 22 9 21 8 20 7 19 6 18 5 17 4 16 3 15 2 14 1 c48 0.1uf + c43 0.1uf + c45 0.1uf + c34 0.1uf + c33 0.1uf + c50 0.1uf + l6 f.b. c35 0.1uf + c52 0.1uf + c40 0.1uf + c32 0.1uf + u9 max232 c1+ 1 c1- 3 c2+ 4 c2- 5 t1o 14 r1i 13 t2o 7 r2i 8 vcc 16 v+ 2 v- 6 gnd 15 t1i 11 r1o 12 t2i 10 r2o 9 c36 0.1uf u10 max232 c1+ 1 c1- 3 c2+ 4 c2- 5 t1o 14 r1i 13 t2o 7 r2i 8 vcc 16 v+ 2 v- 6 gnd 15 t1i 11 r1o 12 t2i 10 r2o 9 c37 0.1uf + c38 0.1uf + u12 max232 c1+ 1 c1- 3 c2+ 4 c2- 5 t1o 14 r1i 13 t2o 7 r2i 8 vcc 16 v+ 2 v- 6 gnd 15 t1i 11 r1o 12 t2i 10 r2o 9 c55 0.1uf + u11 max232 c1+ 1 c1- 3 c2+ 4 c2- 5 t1o 14 r1i 13 t2o 7 r2i 8 vcc 16 v+ 2 v- 6 gnd 15 t1i 11 r1o 12 t2i 10 r2o 9 p1b connector db25 13 25 12 24 11 23 10 22 9 21 8 20 7 19 6 18 5 17 4 16 3 15 2 14 1 u13 max232 c1+ 1 c1- 3 c2+ 4 c2- 5 t1o 14 r1i 13 t2o 7 r2i 8 vcc 16 v+ 2 v- 6 gnd 15 t1i 11 r1o 12 t2i 10 r2o 9 rxda txda nrtsa rxca nctsa ndtra ndcda txca txcb ndcdb ndtrb nctsb txdb rxcb nrtsb rxdb ndsra ndsrb
a a b b c c d d e e 4 4 3 3 2 2 1 1 boot flash rom : 8/16 bit bus width is selectable even odd gnd vss rom.sch 1.0 snds100 (samsung netarm development system) a 7 10 saturd ay, january 16, 1999 samsung electronics co .ltd,. title size document numbe r rev date: sheet of nwbe[0..1] addr4 addr3 addr2 addr7 addr1 addr8 addr10 addr9 addr14 addr13 addr12 addr11 addr15 addr0 addr[0. .18] nwbe0 noe addr5 addr18 addr6 nrcs0 xdata3 xdata2 xdata7 xdata4 xdata0 xdata5 xdata6 xdata1 addr16 addr17 addr4 addr3 addr2 addr7 addr1 addr8 addr10 addr9 addr14 addr13 addr12 addr11 addr15 addr0 addr5 addr18 addr6 xdata8 xdata11 xdata9 xdata13 xdata15 xdata14 xdata10 xdata12 addr16 addr17 nwbe1 xdata[0.. 15] vddd vddd vddd vddd vcc vddd u17 29ee010 a0 12 a1 11 a2 10 a3 9 a4 8 a5 7 a6 6 a7 5 a8 27 a9 26 a10 23 a11 25 a12 4 a13 28 a14 29 a15 3 a16 2 a17 30 a18 1 do0 13 dq1 14 dq2 15 dq3 17 dq4 18 dq5 19 dq6 20 dq7 21 ce 22 oe 24 we 31 vdd 32 gnd 16 u18 29ee010 a0 12 a1 11 a2 10 a3 9 a4 8 a5 7 a6 6 a7 5 a8 27 a9 26 a10 23 a11 25 a12 4 a13 28 a14 29 a15 3 a16 2 a17 30 a18 1 do0 13 dq1 14 dq2 15 dq3 17 dq4 18 dq5 19 dq6 20 dq7 21 ce 22 oe 24 we 31 vdd 32 gnd 16 c81 0.1uf c82 0.1uf noe addr[0.. 18] nwbe[0..1] xdata[0..1 5] nrcs0
a a b b c c d d e e 4 4 3 3 2 2 1 1 noe noe noe noe gnd vss sra m.sch 1.0 snds100 ( samsung netarm development system) b 8 10 saturday, january 16, 199 9 samsung elect ronics co.ltd,. title size document num ber rev date: sheet of xdata0 addr0 cs xdata1 xdata2 xdata3 xdata4 xdata5 xdata6 xdata7 addr1 addr2 addr3 addr4 addr5 addr6 addr7 addr8 addr9 addr10 addr11 addr12 addr13 addr14 addr15 addr16 addr[ 0..16] xdata[0. .31] addr0 cs xdata8 addr1 addr2 addr3 addr4 addr5 addr6 addr7 addr8 addr9 addr10 addr11 addr12 addr13 addr14 addr15 addr16 addr8 addr3 addr15 addr11 addr5 addr4 addr16 addr12 xdata16 addr6 cs addr1 addr9 addr2 addr0 addr13 addr7 addr10 addr14 addr0 cs xdata24 addr1 addr2 addr3 addr4 addr5 addr6 addr7 addr8 addr9 addr10 addr11 addr12 addr13 addr14 addr15 addr16 necs0 necs[0..3] necs1 necs2 necs3 nwbe2 nwbe1 nwbe3 nwbe0 nwbe[0..3] noe xdata9 xdata10 xdata11 xdata12 xdata13 xdata14 xdata15 xdata17 xdata18 xdata19 xdata20 xdata21 xdata22 xdata23 xdata25 xdata26 xdata27 xdata28 xdata29 xdata30 xdata31 cs nrcs4 nrcs2 nrcs[1..5] nrcs5 nrcs3 nrcs1 vddd vddd vddd vddd vddd vddd vddd vddd vcc vddd u19 km6810 00c_55(sop) a0 12 a1 11 a2 10 a3 9 a4 8 a5 7 a6 6 a7 5 a8 27 a9 26 a10 23 a11 25 a12 4 a13 28 a14 3 a15 31 a16 2 cs1 22 cs2 30 oe 24 we 29 d1 13 d2 14 d3 15 d4 17 d5 18 d6 19 d7 20 d8 21 vcc 32 vss 16 u20 km68 1000c_55(sop) a0 12 a1 11 a2 10 a3 9 a4 8 a5 7 a6 6 a7 5 a8 27 a9 26 a10 23 a11 25 a12 4 a13 28 a14 3 a15 31 a16 2 cs1 22 cs2 30 oe 24 we 29 d1 13 d2 14 d3 15 d4 17 d5 18 d6 19 d7 20 d8 21 vcc 32 vss 16 u21 km68 1000c_55(sop) a0 12 a1 11 a2 10 a3 9 a4 8 a5 7 a6 6 a7 5 a8 27 a9 26 a10 23 a11 25 a12 4 a13 28 a14 3 a15 31 a16 2 cs1 22 cs2 30 oe 24 we 29 d1 13 d2 14 d3 15 d4 17 d5 18 d6 19 d7 20 d8 21 vcc 32 vss 16 u22 km6810 00c_55(sop) a0 12 a1 11 a2 10 a3 9 a4 8 a5 7 a6 6 a7 5 a8 27 a9 26 a10 23 a11 25 a12 4 a13 28 a14 3 a15 31 a16 2 cs1 22 cs2 30 oe 24 we 29 d1 13 d2 14 d3 15 d4 17 d5 18 d6 19 d7 20 d8 21 vcc 32 vss 16 c83 0.1uf c84 0.1uf c85 0.1uf c86 0.1uf jp8 header 9x 2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 noe addr[ 0..16] xdata[0. .31] nrcs[1..5] necs[0..3] nwbe[0..3]
a a b b c c d d e e 4 4 3 3 2 2 1 1 uart serial port #0, #1 dsr rxd txd dtr gnd vss dsr rxd txd dtr uart. sch 1.0 snds100 ( samsung netarm development system) b 10 10 saturday, january 16, 199 9 samsung elect ronics co.ltd,. title size document num ber rev date: sheet of uarxd0 uatxd0 uarxd1 uatxd1 vddd vddd vddd vddd vcc vddd c102 0.1uf + c104 0.1uf + c101 0.1uf + c103 0.1uf + c106 330pf c105 330pf c107 330pf c108 330pf c111 0.1uf + c113 0.1uf + c110 0.1uf + c112 0.1uf + c100 0.1uf c109 0.1uf u28 max232 c1+ 1 c1- 3 c2+ 4 c2- 5 t1o 14 r1i 13 t2o 7 r2i 8 vcc 16 v+ 2 v- 6 gnd 15 t1i 11 r1o 12 t2i 10 r2o 9 u29 max232 c1+ 1 c1- 3 c2+ 4 c2- 5 t1o 14 r1i 13 t2o 7 r2i 8 vcc 16 v+ 2 v- 6 gnd 15 t1i 11 r1o 12 t2i 10 r2o 9 p2 connector d b9x2 14 18 13 17 12 16 11 15 10 1 6 2 7 3 8 4 9 5 c118 330pf c117 330pf c115 330pf c116 330pf uatxd0 uarxd0 uatxd1 uarxd1 nuadsr0 nuadtr0 nuadsr1 nuadtr1
a a b b c c d d e e 4 4 3 3 2 2 1 1 uart serial port #0, #1 dsr rxd txd dtr gnd vss dsr rxd txd dtr uart. sch 1.1 snds100 ( samsung netarm development system) b 10 10 friday, ma y 14, 1999 samsung elect ronics co.ltd,. title size document num ber rev date: sheet of uarxd0 uatxd0 uarxd1 uatxd1 vddd vddd vddd vddd vcc vddd c102 0.1uf + c104 0.1uf + c101 0.1uf + c103 0.1uf + c106 330pf c105 330pf c107 330pf c108 330pf c111 0.1uf + c113 0.1uf + c110 0.1uf + c112 0.1uf + c100 0.1uf c109 0.1uf u28 max232 c1+ 1 c1- 3 c2+ 4 c2- 5 t1o 14 r1i 13 t2o 7 r2i 8 vcc 16 v+ 2 v- 6 gnd 15 t1i 11 r1o 12 t2i 10 r2o 9 u29 max232 c1+ 1 c1- 3 c2+ 4 c2- 5 t1o 14 r1i 13 t2o 7 r2i 8 vcc 16 v+ 2 v- 6 gnd 15 t1i 11 r1o 12 t2i 10 r2o 9 p2 connector d b9x2 14 18 13 17 12 16 11 15 10 1 6 2 7 3 8 4 9 5 c118 330pf c117 330pf c115 330pf c116 330pf uatxd0 uarxd0 uatxd1 uarxd1 nuadsr0 nuadtr0 nuadsr1 nuadtr1
ks32c50100/5000a risc microcontroller h ow to use snds100 board 2- 1 2 how to use snds100 board? setup snds100 environments the evaluation environments for snds100 are shown in figure 2-1. serial port(sio-0) on snds100 have to be connected to com port of host pc . this is can be used as console for monitoring and debugging snds100. if you have the emulator like as embeddedice, you can use jtag port on snds100 as the interface for it. evaluating the 10/100m ethernet function , rj45 connector on snds100 can be connected to host pc or hub and switch. connected to host pc, 10 /100m ethernet cable has crossed wire connections because of rj45 connections for snds100 were designed to adapter side. in case of hub/switch, snds100 can be connected to it directly. dc power adapter which have more then dc6v/800ma output characteristics can be used as input power of the snds100 board. this input power regulated to 3.3v and 5.0v for cpu and peripheral device on snds100 board. sio-1 hdlc-a hdlc-b sio-0 rj45 netmcu snds100 board jtag port embeddedice interface unit 10/100m ethernet cable 14-way ribbon jtag cable dc power 6-8v/> 800ma nic(10/100m) rs232 cable for consol com2 dc power 7~9v lpt1 9-pin rs232 cable 25-pin parallel cable (optional) com1 host pc figure 2-1. setup environments for snds100 board
how to use snds100 board ks32c50100/500 0a risc microcontroller 2- 2 ethernet 10/100 base-t connector same connector and pinout for both 10base-t and 100base-tx. (at the network interface cards/hubs) (at the cables) rj45 female connector at the network interface cards and hubs . rj45 male connector at the cables. pin name descriptions 1 tx+ transmit data+ 2 tx- transmit data- 3 rx+ receive data+ 4 n/c not connected 5 n/c not connected 6 rx- receive data- 7 n/c not connected 8 n/c not connected note: tx & rx are swapped on hub
ks32c50100/5000a risc microcontroller h ow to use snds100 board 2- 3 connection methods for utp cable rj45 pins on snds100 is defined to adapter side. so, you can straight connect snds100 to hub through utp cable. in this case, between the snds100 and hub, the pin numbers are correspond to each others. between the snds100 board and nic which is on host pc, you have to connect each other through utp cable which is crossover patch cord. see figure 2-2 (b) rj45 connector ( snds100 ) rj45 connector ( hub ) 1 4 3 2 5 8 7 6 (a) rj45 connector ( snds100 ) rj45 connector ( host pc ) (b) 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 4 3 2 5 8 7 6 figure 2-2. utp cable connections
how to use snds100 board ks32c50100/500 0a risc microcontroller 2- 4 connection configurations for debug consol uart channel 0(sio-0) on snds100 is assigned to debug console port. using this port, you can download executable image code to dram memory from dos command windows of host pc . also you can monitoring and debugging the device from this port with hyper terminal which is windows utility program supported by windows 95 and windows nt. you can communicate through the rs232 cable from uart channel 0 to com1 or com2 which is serial port on host pc. snds100 supplies the 9pin d-sub male connector for communication channel. detail pin configurations for connecting each others as console port be given as bellows: table 2-1. pin connection configurations for console port. snds100 dir host pc descriptions 9pin d-sub male 9pin d-sub male 25pin d-sub male 2. rxd ? 2. rxd 3. rxd receive data 3. txd 3. txd 2. txd transmit data 4. dtr 4. dtr 20. dtr data terminal ready 5. dsr ? 5. dsr 6. dsr data set ready
ks32c50100/5000a risc microcontroller h ow to use snds100 board 2- 5 configuring the hyper terminal ( on windows 95 or nt) to configure the hyper terminal which is windows utility program for serial communications be given on windows 95 or nt, please following steps: 1. running the hyper terminal utility program. window 95 or windows nt start tool bar program accessories hyper terminal group double click hyperterm.exe enter connection name select icon click ok. 2. select com port to communicate with snds100 target board. choose com1 or com2 as the serial communication port click ok 3. set the serial port properties. (see the figure 2-3.) ? bits per second : 115200 bps ? data bits : 8 bits ? stop bits : 1 ? flow control : none figure 2-3. setting port properties
how to use snds100 board ks32c50100/500 0a risc microcontroller 2- 6 configuring the hyper terminal ( on windows 95 or nt) (continued ) 4. select properties menu file properties. 5. choose setting page (figure 2-4) 6. click ascii setup button 7. check ascii setup menus and set (figure 2-5) 8. re-c onnect hyper-terminal to run at new properties ? disconnect: call disconnect ? connect : call call 9. power-on reset or push the reset button on snds100 board ? now, the diagnostic menu is showed on the hyper-terminal (refer to figure 2-6). figure 2-4. choose setting page
ks32c50100/5000a risc microcontroller h ow to use snds100 board 2- 7 figure 2-5. ascii setup menu figure 2-6. snds100 diagnostic window after reset
how to use snds100 board ks32c50100/500 0a risc microcontroller 2- 8 how to build executable download image file execution image file can be built using by arm project manager or makefile. if you want to use arm debugger, you have to build arm image format(aif). any other case, if you want to use only console debugging snds100 board without arm debugger, then binary image file have to be prepared to download directly and execute on target board. first of all, you must download snds100.zip which is evaluation source included boot code from our web site( www.samsungsemi.com ) and also any other utilities and follow up the bellows. it will be helpful to more easily understand the development environments of netmcu series. using arm project manager arm sdt version 2.11a were installed and used for the following procedures. creating a new project to create a new project, following the steps: 1. invoke arm project manager 2. generate a new project file menu new select project form the new dialog box 3. edit new project dialo g box (figure 2-7) ? type : arm executable image ? enter project name and directory 4. when you have created a new project, the information in the project window is displayed in a hierarchical flow diagram. (figure 2-8) ? debug: for creating a target image suitable for debugging, which includes debugging information. ? release: for creating a target image suitable for release, which includes debugging information.
ks32c50100/5000a risc microcontroller h ow to use snds100 board 2- 9 figure 2-7. new project dialog window figure 2-8. project window
how to use snds100 board ks32c50100/500 0a risc microcontroller 2- 10 adding source files to the project to add source files to the project, following the steps: 1. select add files to project from the project menu. 2. select source files to add (*.c and *.s on working directory) setting the options of arm project manager you should set the options on tools menu for setting arm project manager tool.for additional options and descriptions of compiler, assembler, and linker, please refer to the chapter1,2, and 3 of ? arm software development toolkit reference guide ? . setting c compiler option 1. select =armcc option. tools -> configure -> =armcc 2. if the modify warning dialog box pops up, read it, and click yes. 3. modify target page on compiler configuration dialog box as shown in figure 2-9. ? addressing mode: 32 bit ? processor: arm7tm ? byte sex: big endian 4. write option to c&debug page on compiler configuration dialog box as shown in figure 2-10. ? extra command line arguments: - fc 5. click ok.
ks32c50100/5000a risc microcontroller h ow to use snds100 board 2- 11 figure 2-9. compiler configuration: target page
how to use snds100 board ks32c50100/500 0a risc microcontroller 2- 12 figure 2-10. compiler configuration: c & debug page
ks32c50100/5000a risc microcontroller h ow to use snds100 board 2- 13 setting assembler option 1. select < asm>= armasm option. tools -> configure -> < asm>= armasm 2. if the modify warnning dialog box pops up, read it, and click yes. 3. modify target page on assembler configuration dialog box (figure 2-10). ? processor: arm7tm ? byte sex: big endian 4. click ok. figure 2-11. assembler configuration
how to use snds100 board ks32c50100/500 0a risc microcontroller 2- 14 setting link option 1. select armlink option. tools -> configure -> armlink 2. if the modify warning dialog bo x pops up, read it, and click yes. 3. modify output page on linker configuration dialog box (figure 2-12). output formats: absolute aif 4. modify entry and base page on linker configuration dialog box (figure 2-13). ? read-only: 0x1000050 ? read-write: 0x1300000 5. modify imagelayout page on linker configuration dialog box (figure 2-14). ? object file: init.o ? area name: init 4. click ok. figure 2-12. linker configuration: output page
ks32c50100/5000a risc microcontroller h ow to use snds100 board 2- 15 figure 2-13. linker configuration: entry and base page
how to use snds100 board ks32c50100/500 0a risc microcontroller 2- 16 figure 2-14. linker configuration: image layout page
ks32c50100/5000a risc microcontroller h ow to use snds100 board 2- 17 building diag project now, you can start compiling the diag source code in arm project manager and check error message or warning message, and fix problem. if there is no compiling error, executable image file named diag.axf or diag.bin can be generated at working directory. if the generated image format is arm image format(ex. diag.axf), you can execute it by click arm debug icon on windows or typing ? adw diag.axf ? at dos windows. adw is arm debugger execution file. if the generated image format is binary format, then you can use sftp.exe utility which is available at web site in dos windows. it`s usage is described at the end of this section. how to using arm debugger with embedded ice if you have built a diag project without any error, find the executable arm image output file ( diag.axf) on your project sub-directory. then, execute and debug the project. the generated image file will be downloaded by arm debugger through the embeddedice (arm emulator) interfacing jtag port to dram memory on the snds100 target board. next, you can start to debug the downloaded image using arm debugger window(adw). starting arm debugger 1. reset the snds board and the embeddedice interface unit. reset snds (press reset switch) -> reset embeddedice interface unit (press red switch) 2. start arm debugger tool from arm project manager window. project menu -> debug diag.apj also, you can start it at dos windows as you type ? adw diag.axf ? in there. 3. when a rm debugger is started, it will load the image code to armulator (refer to section 1.5). if you ever used arm debugger as a remote debugger, remote debugger warning message dialog box will be displayed. if the remote debugger option is correct, then select yes, otherwise, select no.
how to use snds100 board ks32c50100/500 0a risc microcontroller 2- 18 configuring arm debugger in order to access a remote target, you should configure arm debugger for windows (adw) rather than armulator. the embeddedice interface unit must also be configured for the arm core in the target system (snds100 board). the arm7tdmi core is contained in the KS32C5000 /5000a or ks32c50100 on the snds100 board. arm7tdmi macro cell includes the arm7 core with thumb, debug extensions, and the embeddedice macro cell. to configure arm debugger using the embeddedice interface, following the steps: 1. select configure debugger from the options menu. options -> configure debugger 2. debugger configuration dialog box is displayed (figure 2-15). when you select target page, there are two target environment available as follows. ? armulator: lets you execute the arm program without any physical arm hardware by simulating arm instructions in software. ? remote_a: connects the arm debugger directly to the target board or to an embeddedice unit attached to the target. 3. select remote_a from target environments, and click configure. figure 2-15. debugger configuration: target page
ks32c50100/5000a risc microcontroller h ow to use snds100 board 2- 19 configuring arm debugger ( continued) 4. configure angel remote configuration dialog box(figure 2-16). ? remote connection: select your host and embeddedice communication port configuration. ? select ports and serial line speed. 5. select debugger page from debugger configuration dialog box (figure 2- 17 ) and configure it. ? endian: big ? default memory map: erase the contents of the default memory map. 6. if you click the ok button on debugger configuration dialog box, the debugger will be restarted. the restarting dialog box is displayed and numbers are rapidly changing, indicating that it is reading and writing to target. this means that the executable image file is downloaded to the dram code area. figure 2-16. angel remote configuration
how to use snds100 board ks32c50100/500 0a risc microcontroller 2- 20 configuring arm debugger ( continued) figure 2-17. debugger configuration: debugger page 7. when download is finished, select configure embeddedice from the options menu. options -> configure embeddedice 8. embeddedice configuration dialog box is displayed ( figure 2-18). ? name: arm7tdi 9. if you select the ok button in embeddedice configuration dialog, a new dialog box will be displayed with version number. 10. click ok.
ks32c50100/5000a risc microcontroller h ow to use snds100 board 2- 21 configuring arm debugger ( continued) figure 2-18. embeddedice configuration
how to use snds100 board ks32c50100/500 0a risc microcontroller 2- 22 executing diag project image 1. initialize system variables. after a download, several windows are displayed, such as execution window, console window, and command window. in command window, you must initialize the system variables, "$ semihosting_enabled" and "$ vector_catch", by entering the following command: let $vector_catch=0x00 let $semihosting_enabled=0x00 or, you can initialize these variables as follows: first, create a text file named "armsd.ini", which includes the commands described above. then, enter the following command in the command window (figure 2-19): obey c:\arm211\armsd.ini for more information about these steps, please refer to chapter 6 of "arm software development toolkit user's guide". figure 2-19. arm debugger window(adw): command window 2. execute the program. execute menu -> go 3. now, the downloaded image file( diag.axf) will be run on dram area. diagnostic program running status can be monitored on the current hyper-terminal diagnostic window.
ks32c50100/5000a risc microcontroller h ow to use snds100 board 2- 23 debugging download image in adw stepping through the program to step through the program execution flow, you can select one of the following three options: ? step: advances the program to the next line of code that is displayed in the execution window. ? step into: advances the program to the next line of code that follows all function calls. if the code is in a called function, the function source is displayed in the execution window and the current code. ? step out: advances the program from the current function to the point from which it was called immediately after the function call. the appropriate line of code is displayed in the execution window. setting a breakpoint a breakpoint is the point you set in the program code where the arm debugger will halt the program operation. when you set a breakpoint, it appears as a red marker on the left side of the window. to set a simple breakpoint on a line of code, follow these steps: 1. double-click the line where you want to place the break, or choose toggle breakpoint from the execute menu. the set or edit breakpoint dialog box is displayed. 2. set the count to the required value or expression. (the program stops only when this expression is correct). to set a breakpoint on a line of code within a particular program function: 1. display a list of function names by selecting function names from view menu. 2. double-click the function name you want to open. a new source window is displayed containing the function source. 3. double-click the line where the breakpoint is to be placed, or choose toggle breakpoint from the execute menu. the set or edit breakpoint dialog box appears. 4. set the count to the required value or expression. (the program stops only when this expression is correct). setting a watch point a watch point halts a program when the value of a specified register or a variable changes or is set to a specific number. to set a watch point, follow these steps : 1. display a list of registers, variables, and memory locations you want to watch by selecting the registers, variables, and memory options from the view menu. 2. click the register, variable, or memory area in which you want to set the watchpoint. then choose set or edit watchpoint from the execute menu. 3. enter a target value in the set or edit watchpoint dialog box. program operation will stop when the variable reaches the specified target value.
how to use snds100 board ks32c50100/500 0a risc microcontroller 2- 24 viewing variables, registers, and memory you can view and edit the value of variables, registers, and memory by choosing the related heading from the view menu: ? variables: for global and local variables. ? registers: for the current mode and for each of the six register view modes. ? memory: for the memory area defined by the address you enter. displaying the code interleaved with the disassembly if you want to display the source code interleaved with disassembly, choose toggle interleaving on the options menu. this command toggles between displaying source only and displaying source interleaved with disassembly. when the source code is shown interleaved with disassembly, machine instructions appear in a lighter gray color. for additional information about arm debugger, please refer to chapter 3 of "arm software development toolkit user's guide".
ks32c50100/5000a risc microcontroller h ow to use snds100 board 2- 25 using makefile for image build now, you know how to build image debug and execute use by arm sdt on windows environments. and also, you can build the download image file with makefile on dos environments. using this makefile, you can generate not only arm image format but binary image. if you have no emulator like as embeddedice, you can simply debug and evaluate the target board with this binary image. at dos window, this binary image file can be download to target board through serial cable using sftp.exe utility which is available at our web site. more detail refer to the later in this section. sometimes, it is more convenience for engineer to build image at dos windows not using gui of arm sdt. the sample makefile for diagnostic sources including boot code is shown bellows: makefile ###################################################################### # # # snds100 evaluation board environments setup # # (KS32C5000/KS32C5000a/ks32c50100) # # # ###################################################################### # # # !! edit the bellow the option flag for to fit your system. # # ( please,read "readme.txt" files for guide ) # # # ###################################################################### # ------------------------------------------------------------------ # # arm toolkit environments # ------------------------------------------------------------------ # armpath = c:\arm211a endian = -bi arm_lib = armlib_cn.32b c = armcc assembler = armasm interwork = image = aif cpu_opts = -processor arm7tm -arch 4t device = ks32c50100 #----------------------------------------------------------------# # assembler predefined flags # #----------------------------------------------------------------# #if(rom_address_at_zero) #{ #apdflag = true #memory = -ro 0x0 -rw 0x1300000 #memory = -ro 0x0 #} #else #{ apdflag = false memory = -ro 0x1000050 -rw 0x1300000 #}
how to use snds100 board ks32c50100/500 0a risc microcontroller 2- 26 #----------------------------------------------------------------# # c-predefined option flags # #----------------------------------------------------------------# cpdflags = -d$(device) -dex_uclk #cpdflags = -d$(device) ###################################################################### # # # !!!don't touch this makefile, except for you have to change it .! ! # # # ###################################################################### # # # snds100 evaluation board's makefile for image build # # (KS32C5000/KS32C5000a/ks32c50100) # # # ###################################################################### link = $(armpat h)\bin\armlink asm = $(armpat h)\bin\$(assembler) cc = $(armpath )\bin\$(c) asm4arm = $(armpath)\bin\armasm cc4arm = $(arm path)\bin\armcc asm4thumb = $(armpath)\bin\tasm cc4thumb = $(armpath)\bin\tcc lib = $(armpat h)\lib\$(arm_lib) inc = $(armpath)\include asmflags = $(endian) -g -apcs 3/32bit asmflag_boot = $(endian) -g -apcs 3/32bit -pd "rom_at_address_zero setl {$(apdflag)}" cflags = $(endian) -g -c -fc -apcs 3/32bit $(cpdflags) $(cpu_opts) -i$(inc) #********************************************************************# # link option flags for build rom/dram/ice image # #********************************************************************# link32_5000 = -first init.o(init) $(memory) -o diag -$(image) -bin -nozeropad -symbols diag.sym $(bsplib1) $(bsplib2) $(hdlc) $(arm) $(lib) $(bsptest) link16_5000 = -first tinit.o(init) $(memory) -o tdiag -$(image) -debug -nozeropad -symbols diag.sym $(bsplib1) $(bsplib2) $(hdlc) $(thumb) $(lib) $(bsptest) link32_50100 = -first init.o(init) $(memory) -o diag100 -$(image) -debug -nozeropad -symbols diag.sym $(bsplib1) $(bsplib2) $(hdlc100) $(arm) $(lib) $(bsptest) link16_50100 = -first tinit.o(init) $(memory) -o tdiag100 -$(image) -debug -nozeropad - symbols diag.sym $(bsplib1) $(bsplib2) $(hdlc100) $(thumb) $(lib) $(bsptest) #**********************************************************************# # object codes for build image # #**********************************************************************# thumb = tinit.o tstart.o arm = init.o start.o hdlc = hdlc.o hdlcinit.o hdlclib.o
ks32c50100/5000a risc microcontroller h ow to use snds100 board 2- 27 hdlc100 = hdlcmain.o hdlc100init.o hdlc100lib.o bsplib1 = diag.o down.o flash.o memory.o pollio.o uart.o isr.o timer.o bsplib2 = iic.o system.o dma.o kslib.o mac.o macinit.o maclib.o iop.o bsptest = uart_test.o iic_test.o timer_test.o dhry_1.o dhry_2.o lcd.o diag: $(bsplib1) $(bsplib2) $(hdlc) $(arm) $(bsptest) $(link) $(link32_5000) tdiag: $(bsplib1) $(bsplib2) $(hdlc) $(thumb) $(bsptest) $(link) $(link16_5000) diag100: $(bsplib1) $(bsplib2) $(hdlc100) $(arm) $(bsptest) $(link) $(link32_50100) tdiag100: $(bsplib1) $(bsplib2) $(hdlc100) $(thumb) $(bsptest) $(link) $(link16_50100) #********************************************************************# # build options for boot code # #********************************************************************# init.o: init.s $(asm4arm) $(asmfla g_boot) init.s -o init.o -list init.lst start.o: start.s $(asm4arm) $(asmfla gs ) start.s -o start.o tinit.o: tinit.s $(asm4thubm) $(asmf lag_boot) tinit.s -o tinit.o -list tinit.lst tstart.o: tstart.s $(asm4thubm) $(asmf lags ) tstart.s -o tstart.o #**********************************************************************# # diagnostic source codes # #**********************************************************************# diag.o: diag.c $(cc) $(cflags) -er rors diag.err diag.c down.o: down.c $(cc) $(cflags) -er rors down.err down.c flash.o: flash.c $(cc) $(cflags) -e rrors flash.err flash.c memory.o: memory.c $(cc) $(cflags) - errors memory.err memory.c pollio.o: pollio.c $(cc) $(cflags) -e rrors pollio.err pollio.c uart.o: uart.c $(cc) $(cflags) -er rors uart.err uart.c uart_test.o: uart_test.c $(cc) $(cflags) -er rors uart_ test.err uart_test.c lcd.o: lcd.c $(cc) $(cflags) -er rors lcd.err lcd.c isr.o: isr.c $(cc) $(cflags) -e rrors isr.err isr.c timer.o: timer.c $(cc) $(cflags) -e rrors timer.err timer.c
how to use snds100 board ks32c50100/500 0a risc microcontroller 2- 28 timer_test.o: timer_test.c $(cc) $(cflags) -e rrors timer_test.err timer_test.c iic.o: iic.c $(cc) $(cflags) -e rrors iic.err iic.c iic_test.o: iic_test.c $(cc) $(cflags) -e rrors iic_test.err iic_test.c system.o: system.c $(cc) $(cflags) -e rrors system.err system.c dma.o: dma.c $(cc) $(cflags) -e rrors dma.err dma.c kslib.o: kslib.c $(cc) $(cflags) -e rrors kslib.err kslib.c mac.o: mac.c $(cc) $(cflags) -e rrors mac.err mac.c macinit.o: macinit.c $(cc) $(cflags) -e rrors macinit.err macinit.c maclib.o: maclib.c $(cc) $(cflags) -e rrors maclib.err maclib.c hdlc.o: hdlc.c $(cc) $(cflags) -e rrors hdlc.err hdlc.c hdlcinit.o: hdlcinit.c $(cc) $(cflags) -e rrors hdlcinit.err hdlcinit.c hdlclib.o: hdlclib.c $(cc) $(cflags) -e rrors hdlclib.err hdlclib.c hdlcmain.o: hdlcmain.c $(cc) $(cflags) -e rrors hdlcmain.err hdlcmain.c hdlc100init.o: hdlc100init.c $(cc) $(cflags) -e rrors hdlc100init.err hdlc100init.c hdlc100lib.o: hdlc100lib.c $(cc) $(cflags) -e rrors hdlc100lib.err hdlc100lib.c iop.o: iop.c $(cc) $(cflags) -e rrors iop.err iop.c dhry_1.o: dhry_1.c $(cc) $(cflags) -e rrors dhry_1.err dhry_1.c dhry_2.o: dhry_2.c $(cc) $(cflags) -e rrors dhry_2.err dhry_2.c readme.txt ;/***********************************************************************************************/ ;/* */ ;/* file name version */ ;/* */ ;/* readme.txt snds100 board version 1.0 */ ;/* */ ;/* component */ ;/* */ ;/* */ ;/* description */ ;/* */ ;/* it'll be helpful to build boot rom or download dram image or */ ;/* arm debugger image format for KS32C5000a/ks32c50100. */
ks32c50100/5000a risc microcontroller h ow to use snds100 board 2- 29 ;/* */ ;/* author */ ;/* */ ;/* */ ;/* history */ ;/* */ ;/* name date remarks */ ;/* */ ;/* in4maker 03-10-1999 created initial version 1.0 */ ;/* */ ;/**********************************************************************************************/ 1. how to build diagnostic image files for KS32C5000a/ ks32c50100 ? ********************************************************************** 1) first of all, you have to change the option flags in makefile. option flags are as follows: ********************************************************************** (1) arm sdt environment setup & select device assign arm sdt toolkits installed directory path to armpath. and also select used device as like KS32C5000a or ks32c50100 +------------------------------------------------------------------------------------------+ armpath = e:\arm211a device = ks32c50100 +--------------------------------------------------------------+ (2) c-predefined option flags. +-------------------------------------------------------------------------------------------------+ + c-predefined option flags + +-------------------------------------------------------------------------------------------------+ + [little ] this flag have to be defined for the device to + + operate in little endian mode. + + hdlc ,mac block will be affected by this flag. + + [ex_uclk ] using for external uart clock [usage: -dex_uclk] + + [phy_100m ] configure phy to 100mbps + + [snds1_2 ] have to be defined using snds ver1.2 board with + + KS32C5000a without revise the current diagnostic + + source code. + +-------------------------------------------------------------------------------------------------+ cpdflags = -d$(device) -dex_uclk +-------------------------------------------------------------------------------------------------+ (3) define image format as like arm/thubm and big/little +-------------------------------------------------------------------------------------------------+ thumb(big/little) arm(big/little) +-------------------------------------------------------------------------------------------------+ armlib = armlib.16b/armlib.16l armlib.32b/armlib.32l c = tcc armcc assembler = tasm armasm interwork = / interwork
how to use snds100 board ks32c50100/500 0a risc microcontroller 2- 30 cpu_opts = -processor arm7tm -arch 4t +--------------------------------------------------------------+ (4) to build boot rom image +--------------------------------------------------------------+ image = bin apdflag = true memory = -ro 0x0 -rw 0x1000050 +--------------------------------------------------------------+ (5) to build download dram image +--------------------------------------------------------------+ image = bin apdflag = flase memory = -ro 0x1000050 -rw 0x13000000 +--------------------------------------------------------------+ (6) to build arm debugger image +--------------------------------------------------------------+ image = aif apdflag = flase memory = -ro 0x1000050 -rw 0x13000000 +--------------------------------------------------------------+ ********************************************************************** 2) sysconf.h if you want to change the device's mode like as uart baud rate ,iic serial clock frequency, internal system clock( fmclk) etc, please update this file. ********************************************************************** 3) snds.a snds100 board memory configurations and memory map can be changed by this file. where, the fmclk also have to be updated to same value as fmclk defined at sysconf.h file. ******* * end of readme.txt **********************************************************
ks32c50100/5000a risc microcontroller h ow to use snds100 board 2- 31 now, you have created makefile to build image for your target systems. and then, you have to compile and link using this file by armmake in dos windows. first of all, you have to configure the arm project manager environments(refer to using arm project manager to build image) because its default option values are effects on when run the armmake with makefile . its ready to build image in dos windows . there are four cases as follows: 1. to build 32bit arm image for KS32C5000/5000a, armmake diag 2. to build 16bit thumb image for KS32C5000/5000a. armmake tdiag 3. to build 32bit arm image for ks32c50100, armmake diag100 4. to build 16bit thumb image for ks32c50100. armmake tdiag100 after this is done with no compile and link error, the following files will be generated at your working directory. diag /diag100/tdiag/tdiag100 : executable image file which will be arm or binary image format. diag.sym : symbol file < file _name>.o : object file < file _name>.err : error and warning list files. if you have emulator (ex : embeddedice) or angel potted rom, you can use arm debugger window(adw) .if not, you can download executable binary image file to targets by sftp.exe which is ours program tips. please refer to the next paragraph.
how to use snds100 board ks32c50100/500 0a risc microcontroller 2- 32 downloading executable binary image file without adw without a emulator(ex, embeddedice), you can download a binary image file through the serial cable to target. first of all, you ought to get download utility, sftp.exe, from our web sites . to download a executable binary file, following the steps: 1. select user pgm to download item on the snds100 console(hyper-terminal) menu . it is referred to figure 2-22. figure 2-22. download executable binary image on snds100 board
ks32c50100/5000a risc microcontroller h ow to use snds100 board 2- 33 downloading executable binary image file without adw (continued ) 2. start download the binary image file on host computer .(refer to figure 2-21) ` sftp.exe` is used to download binary image file to target. this execution file is compiled at window95, and the compiler is `visual c++ ` if you are in a different environment, you should recompile the serial download utility source code in your environments. more detail information about `sftp.exe` is described later this chapter. if you already ha ve the utility tips, now, you can send the image file from com1 or com2 port on host pc through the serial cable to console port(default, uart channel 0, sio-0) on snds100. for example, if the uart baud rate is 125200 on snds100, the serial cable is connected from com1 to sio-0, then you have to type ` dos> sftp 1 diag100 ` on dos window `s command prompt. usage : sftp example : dos> sftp 1 diag100 figure 2-21. start download binary image file to target on host computer 2. when the download is finished without any error, press any key to start the download user binary image file on snds100 target board. now, you can simply evaluating and verifying the downloaded applications on snds100.
how to use snds100 board ks32c50100/500 0a risc microcontroller 2- 34 fusing boot rom image to flash(eeprom) you can update the boot rom on snds100 into your new boot image include applications using flash download program which is included in diagnostic code. (please, visit our web site to download this source codes). sst flash device used as boot eeprom on snds100 board. so, the flash program in diagnostic code is for the sst device. if you want to use any other vendor ? s flash device, you have to programming for that to fuse the application to flash memory without rom writer. the above case is just only for updating boot rom on snds100 board. if you have an emulator(embeddedice), you can fuse the boot & applications through the jtag port to flash device on board without boot rom. in this case, the snds100 memory map of the cpu(KS32C5000/5000a/50100) have to be configured by adw. more detail will be described in this section. update boot rom on snds100 board first of all, you have to prepare the dram image file which will be used to fuse new boot rom image or applications to flash memory on snds100 board. to build rom or dram image, please refer to ? using makefile for image build ? section of this chapter. on snds100 board, the bus width of boot rom can be extended to 16bit. actually, the bus width of rom bank0(boot rom bank) can be configured by b0size0(pin 73) and b0size1(pin 74), but you have to edit the flash.h file to modify the bus width of rom bank0 as same value as it. detail flow charts for fusing eeprom are given here. and also the procedure according to that is following: 1. open flash.h file for to update the bus width of rom bank0(boot rom). for example, if you want to use 16bit flash device, then modify the define statement to ? #define b0size b0size _short ? in flash.h file. 2. build dram image file. please refer to ? using makefile for image build ? section for more detail dram image build. 3. download dram image. firstly, you have to enter a character `p` to select user pgm download item on console terminal (hyper terminal). and then you can send dram image file to target board on dos prompt. dos> sftp 1 diag100 4. execute download image. after the dram image is downloaded to dram successfully, press any key to restart the target board. now, the downloaded dram program is running on dram area. next, you have to enter a character `f ` to download the new boot rom image or applications to dram user area.
ks32c50100/5000a risc microcontroller h ow to use snds100 board 2- 35 reset snds100 1. modify the bus width (flash.h) 2. build dram image 3. download dram image download ok? 4. execute download image 5. build new rom image 6. download new rom image download ok? 7. enter eeprom address 8. select eeprom type 9. waiting for eeprom write done restart snds100 yes yes figure 2-22. fusing flow to update boot rom
how to use snds100 board ks32c50100/500 0a risc microcontroller 2- 36 update boot rom on snds100 board ( continued ) 5. build new rom image. this image is for the new boot code or applications. it also refer to `using makefile for image build` section. 6. download new rom image. this new rom image or applications will be downloaded to dram user area and also fused to flash device by flash write program running on dram. 7. enter eeprom address .(figure 2-23) if there is no error for downloading, the console (hyper terminal) request to enter the eeprom load address which is default zero. after this, select eeprom type menu is displayed on console window. 8. select eeprom type .(figure 2-23) 9. waiting for eeprom write is done. 10. now, press reset button on snds100 target board to restart it.
ks32c50100/5000a risc microcontroller h ow to use snds100 board 2- 37 figure 2-23. start flash download program
how to use snds100 board ks32c50100/500 0a risc microcontroller 2- 38 figure 2-24. finished flash download program
ks32c50100/5000a risc microcontroller h ow to use snds100 board 2- 39 serial download program on host computer we provide the download utility for dos. this program tips which are compressed into serial.zip file are available on our web site, ( www.samsungsemi.com ). in this zip file, the ? serial.c ? which is main source code is for to manipulate binary data , and the ? trans.c ? for to manipulate the serial communications of host computer. we compiled this source code by ? visual c++ ? and generated execution file, sftp.exe. using this download utility tips, you can download executable binary image for rom, dram to snds100 target board. this utility tips is just only for dos. so, if you want to send binary image file to target, you have to run this tips on dos prompt. it ? s usage is ? dos> sftp ? . binary data transfer format to transfer a file to target, the serial transfer utility program for host computer and the flash down program in diagnostic code for snds100 use any transfer format which is shown in figure 2-25. length (8 bytes) data (variable) crc (8 bytes) figure 2-25. binary data transfer format where the length field is only data(download file) size. length and crc field is calculated by download utility program. crc check for error check we use crc check method for error check, the crc check use ccitt polynomial, and we check all 8-bit data for each character. code for crc calculation for ( j = 0 ; j < 8 ; j++ ) { checksum <<= 1 ; if( chardata & 0x0080 ) checksum ^= ccitt_polynom ; chardata <<= 1 ; }
how to use snds100 board ks32c50100/500 0a risc microcontroller 2- 40 data transfer flow file transfer flows are shown in figure 2-26. where the data(file) is an executable binary rom or dram image or general text file. start file transfer prepare the text or rom,dram image file run serial file transfer program (usage: dos>sftp 1 image) open serial port (com1 or com2) open file for transfer file open error? calcurate file size send file size to target wait 3 second send file to target calculate crc value file size? send crc value print error message & exit error < = transfer done figure 2-26. file transfer flow
ks32c50100/5000a risc microcontroller d iagnostic source code 3- 1 3 diagnostic source c odes the snds100 programmer ? s model the diagnostic code routines have been written to give practical examples of writing code and evaluating snds100 (samsung network development system) board. snds100 is the target board of the netmcu-i series like as KS32C5000/5000a/50100 which are embedded controller for network solutions based on arm7tdmi. this section will give you a brief descriptions about how to control the embedded functional blocks and also how to evaluate the snds100 board. hardware overview ? boot rom: 16bit data bus, 1mbit eeprom *2, extent to 4mbit *2, located at rom bank0 ? dram type: normal/edo dram for KS32C5000/5000a, normal/edo or syncdram for ks32c50100. dram bank0 used. ? console: uart channel 0(sio-0) used. ? ethernet: rj45 connector, mii interface, 10/100mbps can be configured by auto-negotiation. ? jtag: embedded ice or emulator can be interfaced with this for system debuging. system memory map the snds100 board has 2 rom sockets which can be used to boot rom. it ? s data bus size can be configured to 8bit or 16bit by the b0size[1:0] pins which can be controlled by switch. for the code development, snds100 board support syncdram into component type and also one dram simm sockets. there are all located on dram bank 0. it ? s means that two dram memory have to be selected alternatively according to the kind of attached devices. KS32C5000/5000a only support normal/edo dram so that the dram simm only available for it. in case of ks32c50100, both memory type can supported. so you can select dram simm or syncdram by jumper on snds100. the netmcu-i have a total 16m word memory space. each memory banks can be located anywhere within a this address range by setup the appropriate memory control registers. the data bus size of each bank also can be configured by bus control registers. the system configuration register (syscfg) also used to configure the start address of the special register, the base address of the internal sram, and also control the write buffer, cache, stall, cache mode. the specatial register ? s address area is fixed at 64kbytes. it ? s initial value is 0x3ffff91. you can use the internal 8-kbytes sram as a cache using cache control bit in syscfg register. please refer to user ? s manual for more details. for the direct memory access, you have to configure this area as non-cachable region as set the bit [21] of memory access address.
diagnostic source code ks32c50100/5000a risc microcontroller 3 - 2 system memory map rom bank0 (boot rom) dram bank0 (4mbytes) ext i/o bank0 ext i/o bank1~3 rom bank1~5 not used not used not used internal sram special register not used 0x000_0000 0x100_0000 0x020_0000 0x140_0000 0x360_0000 0x3ff_0000 0x3fe_0000 0x100_0000 0x100_0050 0x140_0000 exception handler vector table code area (application) stack area user area dram bank0 figure 3-1. snds100 system memory map
ks32c50100/5000a risc microcontroller d iagnostic source code 3- 3 data structures of dram bank0 the snds100 system memory allocation table is configured by the compiler. figure 3-2 shows the data structures of dram bank0. 0x100_0000 0x100_0050 0x140_0000 exception handler vector table code area (application) data r/w area & stack area user area dram bank0 non-zero initialized global variable zero initialized global variable image$$rw$$base 0x130_0000 0x130_0000 image$$zi$$base/ c$$zidata$$base c$$zidata$$limit system stack area image$$zi$$limit/ image$$rw$$limit user area 0x140_0000 figure 3-2. data structures of dram bank0
diagnostic source code ks32c50100/5000a risc microcontroller 3 - 4 boot procedures after a power on reset or a reset signal input, the netmcu device on snds100 access the rom located at address 0x0. this rom is written to boot code initializing the system configuration and executing a diagnostic code for evaluation. figure 3-3 shows the boot processing flow by boot rom. the start-up code for booting process is programed by assembler code and the diagnostic by c-source code. start-up (power on/reset) define entry point initialize stack pointer sdram? normal/edo dram & system memory map is configured noraml/edo edo dram r/w test from dram_base r/w ok? sync dram & system memory map is configured exception vector table setup initialize the r/w memory area required by c-code yes no yes change the processor to user mode call c_entry programmed by assemble code c_entry() initialize the critical i/o devices like as interrupt ,uart,mac,hdlc, iic,lcd,phy,timer etc programmed by c-code print memessage to console select test items by key input from console port download? download user image from host pc to target crc ok? execute the selected item yes re-boot figure 3-3. the boot processing flows of boot rom.
ks32c50100/5000a risc microcontroller d iagnostic source code 3- 5 exception handling netmcu devices have seven type of exceptions as shown in table 3-2. more details about exceptions refer to the document, ? arm software development toolkit user guide, section 10 ? . if an exception occurs, netmcu devices act on it for handling which flows are described at figure 3-4. table 3-2. exception handling priorities exceptions descriptions vector address priority reset cpu reset input or power on reset 0x00 1 undefined undefined instruction 0x04 6 swi user-defined synchronous interrupt 0x08 6 prefetch abort prefetch from illegitimate address 0x0c 5 data abort data load/store at an illegitimate address 0x10 2 irq normal interrupt 0x18 4 fiq fast interrupt 0x1c 3
diagnostic source code ks32c50100/5000a risc microcontroller 3 - 6 exception occurs action on entering an exception: - store the return address(lr=pc) - copies cpsr into the appropriate spsr - set cpsr mode bit depends on exceptions - set the pc to the vector address branch to the exception handler routines fetch exception handler entry from the exception vector table on dram get the interrupt service index value use by intoffset register. fetch the interrupt service entry address in the interrupt vector table. branch to the interrupt service routine in interrupt service routine: - clear pending bit - execute an interrupt service action on leaving an exception: - moves lr,minus offset where appropriate ,to the pc. - copies spsr back to cpsr - clears the interrupt disable flags, if they were set on entry return arm7tdmi netmcu h/w & s/w arm7tdmi figure 3-4. exception handling flows of netmcu devices
ks32c50100/5000a risc microcontroller d iagnostic source code 3- 7 structures of diagnostic codes table 3-1 shows the structures of diagnostic source codes. these sources are useful for evaluate snds100 target board. and also, it will be helpful for you to understand our netmcu devices which have many embeded control block. table 3-1. diagnostic code structure /* boot codes */ init ; init.s, snds.a, memory.a, snds.h /* diagnostic source codes for evaluating the target board */ c_entry() ; diag.c, diag.h, kslib.c, kslib.h, sysconf.h |--------- memtestdiag() ; memory.c, memory.h |--------- cachetestdiag() ; system.c, system.h |--------- dmatestdiag() ; dma.c, dma.h |-------- timertestdiag() ; timer.c, timer.h,timer_test.c |-------- mactestdiag() ; mac.c, mac.h, macinit.c, maclib.c |-------- hdlctestdiag() ; hdlc.c, hdlc.h, hdlcinit.c, hdlclib.c for KS32C5000/5000a | ; hdlcmain.h, hdlcmain.c, hdlc100init.c, hdlc100lib.c for 50100 |-------- i2ctestdiag() ; iic.c, iic.h, iic_test.c |-------- uarttestdiag() ; uart.c, uart.h, uart_test.c |-------- iofuncdiag() ; iop.c, iop.h |-------- downloaddiag() ; down.c, down.h |-------- fusingdiag() ; flash.c, flash.h |-------- lcdonlytestmode() ; lcd.c, lcd.h |-------- banchmarkdiag() ; dhry_1.c, dhry_2.c, dhry.h boot codes memory.a snds100 board system memory map snds.a assembler code header file for netmcu-i(KS32C5000/5000a/50100). defined equ table in this file will be helpful for you to configure and initialize the system memory map. snds.h c- header file of netmcu-i for snds100 target board. system registers are defined in this file. init.s assemble code for the booting procedure. it performs the stack initialization, system memory configuration, exception vector table setup and c required memory initailiztion. after this boot procedure is done, it branched to c_entry point to run appliations.
diagnostic source code ks32c50100/5000a risc microcontroller 3 - 8 diagnostic c-source codes sysconf.h , system configuration header file. this file include the peripheral control parameters like as uart baudrate, iic serial frequ ency, operating frequency etc,. while you evaluate the target board, you want to change the above parameters frequently system.c, system.h this example c source code shows the usage of cache and internal sram. cpu clock control using the clock control register is also evaluated. dma.c, dma.h data transfer memory to memory, uart to memory, memory to uart . timer.c, timer.h usage for timer functions. mac.c ,mac.h there are many functions for receiving and transmitting ethernet frames such as rx/tx macinit.c, maclib.c descriptors, station management, etc. external and internal loopback programs are also included here for the perpose of diagnostic test the mac control block. hdlc.c, hdlc.h diagnostic code for KS32C5000/5000a hdlc (high-level data link control) control hdlcinit.c,hdlclib.c functions. hdlcmain.c , diagnostic code for ks32c50100 hdlc (high-level data link control) control functions. hdlcmain.h hdlc100init.c , hdlc100lib.c iic.c, iic.h t o evaluate the iic-bus control block, an samsung iic serial eeprom, ks24c64 were used. uart.c, uart.h external loop back using interrupt mode and internal loop back using polling mode codes pollio.c are described here. there are also some libraries for standard input through uart such as get_byte, put_byte,put_string, print etc. iop.c, iop.h i/o ports input/output and shared functions such as external interrupt, external dma request and acknowlege, timer-out put test c odes are described here. lcd.c, lcd.h snds100 support the lcd display pannel. many lcd display functions are implemented. snds100 target board can be evaluated at stand alone using lcd display as console and key pad on target without a connection from the host pc to uart . dhry_1.c, dhry_2.c this is a benchmarking program that measure the system performance (dhrystone vax dhry.h mips).
ks32c50100/5000a risc microcontroller d iagnostic source code 3- 9 down.c, down.h , this code includes functions for dowmloading user program through uart cha nnel from start.s host pc. downloaded user program will be located in a given area on dram. flash.c, flash.h after the code debugging is finished, applications can be written to eeprom on the snds100 board directly by this program. these codes are only for the sst eeprom. for using anyother vendor ? s eeprom, you yourself have to prepare the eeprom write program. program tips for download utility (for dos) serial.c, serial.h, compile this tips using visual c++ 4.0. after that you can run this tips on dos window tran.c to transfer image file to target from the serial port (com1/com2) of the host pc through serial cable to uart channel on snds100 board.
diagnostic source code ks32c50100/5000a risc microcontroller 3 - 10 code descriptions for each function modules initial start-up(boot) code ? init.s ? is assembler code for boot process. system memory map configurations, stack initialization, exception vector table generation, c-required memory initialization can be done by this start-up code. also "arm software development toolkit user guide" can be referenced to help writing a code to rom. figure 3-1,3-2 shows the memory map & usage of the snds100 board. listing 3-1. (init.s) ; --- define entry point export __main ; defined to ensure that c runtime system __main ; is not linked in entry when the compiler compiles the function main(), it generates a reference to the symbol __main to force the linker to include the basic c runtime system from the semi-hosted c library. if the semi-hosted c library is not linked while having the main() function, an error may occur. to avoid an confusion, you are advised to call something other than main(), such as c_entry() or rom_entry() as the c entry point, when building a rom image listing 3-2.(init.s) ; --- setup interrupt / exception vectors if :def: rom_at_address_zero ; if the rom is at address 0 this is just a sequence of branches b reset_handler b undefined_handler b swi_handler b prefetch_handler b abort_handler nop ; reserved vector b irq_handler b fiq_handler else ; otherwise we copy a sequence of ldr pc instructions over the vectors ; (note: we copy ldr pc instructions because branch instructions ; could not simply be copied, the offset in the branch instruction ; would have to be modified so that it branched into rom. also, a ; branch instructions might not reach if the rom is at an address ; > 32m). mov r8, #0 adr r9, vector_init_block ldmia r9!, {r0-r7} stmia r8!, {r0-r7} ldmia r9!, {r0-r7}
ks32c50100/5000a risc microcontroller d iagnostic source code 3- 11 stmia r8!, {r0-r7} ; now fall into the ldr pc, reset_addr instruction which will continue ; execution at 'reset_handler' vector_init_block ldr pc, reset_addr ldr pc, undefined_addr ldr pc, swi_addr ldr pc, prefetch_addr ldr pc, abort_addr nop ldr pc, irq_addr ldr pc, fiq_addr reset_addr dcd reset_handler undefined_addr dcd undefined_handler swi_addr dcd swi_handler prefetch_addr dcd prefetch_handler abort_addr dcd abort_handler dcd 0 ; reserved vector irq_addr dcd irq_handler fiq_addr dcd fiq_handler endif ;========================================================== ; the default exception handler vector entry pointer setup ;========================================================== fiq_handler sub sp, sp, #4 stmfd sp!, {r0} ldr r0, =handlefiq ldr r0, [r0] str r0, [sp, #4] ldmfd sp!, {r0, pc} irq_handler sub sp, sp, #4 stmfd sp!, {r0} ldr r0, =handleirq ldr r0, [r0] str r0, [sp, #4] ldmfd sp!, {r0, pc} prefetch_handler sub sp, sp, #4 stmfd sp!, {r0} ldr r0, =handleprefetch ldr r0, [r0] str r0, [sp, #4] ldmfd sp!, {r0, pc}
diagnostic source code ks32c50100/5000a risc microcontroller 3 - 12 abort_handler sub sp, sp, #4 stmfd sp!, {r0} ldr r0, =handleabort ldr r0, [r0] str r0, [sp, #4] ldmfd sp! , {r0, pc} undefined_handler sub sp, sp, #4 stmfd sp!, {r0} ldr r0, =handleundef ldr r0, [r0] str r0, [sp, #4] ldmfd sp!, {r0, pc} swi_handler sub sp, sp, #4 stmfd sp!, {r0} ldr r0, =handleswi ldr r0, [r0] str r0, [sp, #4] ldmfd sp!, {r0, pc} listing 3-3. (memory.a) ;/*************************************************************************/ ;/* dram memory bank 0 area map for exception vector table */ ;/* and stack, user code area. */ ;/*************************************************************************/ dram_base equ 0x1000000 ;dram_limit equ 0x1800000 dram_limit equ 0x1400000 ;------------------------------------------------- exceptionsize equ 0x50 ; exception vector addr pointer space sysstacksize equ 1024 * 8 ; define 8k system stack exceptiontable equ dram_base + exceptionsize ;/* exception handler vector table */ ^ dram_base handlereset #4 handleundef #4 handleswi #4 handleprefetch #4 handleabort #4 handlereserv #4 handleirq #4 handlefiq #4
ks32c50100/5000a risc microcontroller d iagnostic source code 3- 13 ;/* system user code area */ ^ dram_base+exceptionsize ;=0x1000050 usercodearea #4 locating the boot rom at address zero, the pre-defined symbol, rom_at_address_zero have to be assigned to logical value true. an application image with boot procedure can be downloaded and run on dram as assign logical value false to rom_at_address_zero on debugging stage. in this case, the boot sequence of download image is not located at address zero so that the exception vector table on boot rom have to be linked to exception vector table on dram . at the above boot sequence shows that the both case whether boot code located at address zero or not are same as that have exception vector table located on dram region. it will be convenient for you to debug an application and build to rom image with same code. but, it also caused to be a latency problem handling the exceptions. to avoid the exception latency problems and slow execution of application on rom, rom image can be copied to dram and change the memory map to locate the dram at address zero at power on reset booting procedures. more details will be described in this section. listing 3-4.(init.s) area main, code, readonly ;========================================================== ; the reset entry point ;========================================================== reset_handler ;/* reset entry point */ [ rom_at_address_zero | ldr r0, =handleswi ; swi exception table address ldr r1, =systemswihandler str r1, [r0] swi 0xff ;/* call swi vector */ ] the code(listing 3-4) is for the boot processing of download image. after the boot sequence of boot rom is done, the cpu status is in user mode. the boot processing can be made only in supervisor mode. so, to execute the boot sequence by the download application, cpu mode have to changed to supervisor mode using call swi handler.
diagnostic source code ks32c50100/5000a risc microcontroller 3 - 14 listing 3-5.(init.s) ;===================================== ; initialize stack pointer ;===================================== initialize_stack mrs r0, cpsr bic r0, r0, #lockout | mode_mask orr r2, r0, #usr_mode orr r1, r0, #lockout | fiq_mode msr cpsr, r1 msr spsr, r2 ldr sp, =fiq_stack orr r1, r0, #lockout | irq_mode msr cpsr, r1 msr spsr, r2 ldr sp, =irq_stack orr r1, r0, #lockout | abt_mode msr cpsr, r1 msr spsr, r2 ldr sp, =abt_stack orr r1, r0, #lockout | udf_mode msr cpsr, r1 msr spsr, r2 ldr sp, =udf_stack orr r1, r0, #lockout | sup_mode msr cpsr, r1 msr spsr, r2 ldr sp, =sup_stack ; change cpsr to svc mode
ks32c50100/5000a risc microcontroller d iagnostic source code 3- 15 listing 3-6. (init.s) ;/***************************************************/ area sys_stack, noinit ;/***************************************************/ % usr_stack_size usr_stack % udf_stack_size udf_stack % abt_stack_size abt_stack % irq_stack_size irq_stack % fiq_stack_size fiq_stack % sup_stack_size sup_stack ;/***************************************************/ end system stack will be allocated to non-initialized r/w area of dram by arm linker when the image is build. listing 3-7. (init.s) ;===================================== ; setup special register ;===================================== ldr r0, =0x3ff0000 ; read syscfg register v alue ldr r1,[r0] ; to identify dram type ldr r2, =0x80000000 and r0, r1, r2 ; mask dram type mode bit cmp r0, r2 bne edo_dram_configuration b sync_dram_configuration ; only when ks32c50100 ;================================================== ; special register configuration for edo mode dram ; when KS32C5000 and ks32c50100 ;================================================== edo_dram_configuration ldr r0, =0x3ff0000 ldr r1, =0x3ffff90 ; se tvalue = 0x3ffff91 str r1, [r0] ; cache,wb disable ; start_addr = 0x3ff00000 ;rom and ram configuration(multiple load and store) adrl r0, systeminitdata ldmia r0, {r1-r12} ldr r0, =0x3ff0000 + 0x3010 ; romcntr offset : 0x3010 stmia r0, {r1-r12}
diagnostic source code ks32c50100/5000a risc microcontroller 3 - 16 ldr r1,=dram_base str r1,[r1] ; [dram_base] = dram_base ldr r2,[r1] ; read dram data cmp r2,r1 beq exception_vector_table_setup ;================================================== ; special register configuration for sync dram ; only when ks32c50100 ;================================================== sync_dram_configuration ldr r0, =0x3ff0000 ldr r1, =0x83ffff90 ; setvalue = 0x83ffff91 str r1, [r0] ; cache,wb disable ; start_addr = 0x3ff00000 ;rom and ram configuration(multiple load and store) adrl r0, systeminitdatasdram ldmia r0, {r1-r12} ldr r0, =0x3ff0000 + 0x3010 ; romcntr of fset : 0x3010 stmia r0, {r1-r12} ks32c50100 support sdram in addition to normal/edo dram. both memory types are mounted on the snds100 target board so that you can choose the memory types alternatively by set of jumper. (jp1,jp2). after the jumper setting and power on reset, the mounted memory type can be decided by the above routine checking the memory mode bit of syscfg register or testing the default configured memory at first. now, the system stack initialization and system memory map configuration is done. listing 3-8.(init.s) ;============================= ; exception vector table setup ;============================= exception_vector_table_setup ldr r0, =handlereset ; exception vector table memory loc. ldr r1, =exceptionhandlertable ; exception handler assign mov r2, #8 ; number of exception is 8 exceptloop ldr r3, [r1], #4 str r3, [r0], #4 subs r2, r2, #1 ; down count bne exceptloop the c-code exception handlers will be setup to exception vector table on dram using the table of exceptionhandlertable.
ks32c50100/5000a risc microcontroller d iagnostic source code 3- 17 listing 3-9. (init.s) ;=========================================== ; exception vector function definition ; consist of function call from c-program. ;=========================================== systemundefinedhandler import isr_undefhandler stmfd sp!, {r0-r12} b isr_undefhandler ldmfd sp!, {r0-r12, pc}^ systemswihandler stmfd sp!, {r0-r12,lr} ldr r0, [lr, #-4] bic r0, r0, #0xff000000 cmp r0, #0xff beq makesvc ldmfd sp!, {r0-r12, pc}^ makesvc mrs r1, spsr bic r1, r1, #mode_mask orr r2, r1, #sup_mode msr spsr, r2 ldmfd sp!, {r0-r12, pc}^ systemprefetchhandler import isr_prefetchhandler stmfd sp!, {r0-r12, lr} b isr_prefetchhandler ldmfd sp!, {r0-r12, lr} ;add sp, sp, #4 subs pc, lr, #4 systemaborthandler import isr_aborthandler stmfd sp!, {r0-r12, lr} b isr_aborthandler ldmfd sp!, {r0-r12, lr} ;add sp, sp, #4 subs pc, lr, #8 systemreserv subs pc, lr, #4 systemirqhandler import isr_irqhandl er stmfd sp!, {r0-r12, lr} bl isr_irqhandler ldmfd sp!, {r0-r12, lr} subs pc, lr, #4
diagnostic source code ks32c50100/5000a risc microcontroller 3 - 18 systemfiqhandler import isr_fiqhandler stmfd sp!, {r0-r7, lr} bl isr_fiqhandler ldmfd sp!, {r0-r7, lr} subs pc, lr, #4 system exception handlers are consist of function call from c-code( isr.c ). this handler function can be referenced by exceptionhandlertable.
ks32c50100/5000a risc microcontroller d iagnostic source code 3- 19 listing 3-10. (init.s) area romdata, data, readonly ;====================================================== ; dram system initialize data(KS32C5000 and ks32c50100) ;====================================================== systeminitdata dcd rextdbwth ; dram1(half), rom5(byte), rom1(half), else 32bit dcd rromcon0 ; 0x0000000 ~ 0x01fffff, rom0,4mbit,2cycle dcd rromcon1 ; dcd rromcon2 ; 0x0400000 ~ 0x05fffff, rom2 dcd rromcon3 ; 0x0600000 ~ 0x07fffff, rom3 dcd rromcon4 ; 0x0800000 ~ 0x09fffff, rom4 dcd rromcon5 ; dcd rdramcon0 ; 0x1000000 ~ 0x13fffff, dram0 4m, dcd rdramcon1 ; 0x1400000 ~ 0x17fffff, dram1 4m, dcd rdramcon2 ; 0x1800000 ~ 0x1efffff, dram2 16m dcd rdramcon3 ; 0x1c00000 ~ 0x1ffffff dcd rrefextcon ; external i/o, refresh ;====================================================== ; sdram system initialize data (ks32c50100 only) ;====================================================== systeminitdatasdram dcd rextdbwth ; dram1(half), rom5(byte), rom1(half), else 32bit dcd rromcon0 ; 0x0000000 ~ 0x01fffff, rom0,4mbit,2cycle dcd rromcon1 ; dcd rromcon2 ; 0x0400000 ~ 0x05fffff, rom2 dcd rromcon3 ; 0x0600000 ~ 0x07fffff, rom3 dcd rromcon4 ; 0x0800000 ~ 0x09fffff, rom4 dcd rromcon5 ; dcd rsdramcon0 ; 0x1000000 ~ 0x13fffff, dram0 4m, dcd rsdramcon1 ; 0x1400000 ~ 0x17fffff, dram1 4m, dcd rsdramcon2 ; 0x1800000 ~ 0x1efffff, dram2 16m dcd rsdramcon3 ; 0x1c00000 ~ 0x1ffffff dcd rsrefextcon ; external i/o, refresh ;=========================================== ; exception handler vector table entry point ;=========================================== exceptionhandlertable dcd usercodearea dcd systemundefinedhandler dcd systemswihandler dcd systemprefetchhandler dcd systemaborthandler dcd systemreserv dcd systemirqhandler dcd systemfiqhandler align
diagnostic source code ks32c50100/5000a risc microcontroller 3 - 20 the above data table for exception handler, system memory map will be defined at rom or dram read only area. system initialization data table named systeminitdata and systeminitdatasdram contain the register setting values for memory access cycle, refresh cycle, data bus width etc. you can update and change this parameters easily using equ table . ( snds.a ) listing 3-11. (snds.a) ;/*************************************************************************/ ;/* format of the program status register */ ;/*************************************************************************/ fbit equ &40 ibit equ &80 lockout equ &c0 ;interrupt lockout value lock_msk equ &c0 ;interrupt lockout mask value mode_mask equ &1f ;processor mode mask udf_mode equ &1b ;undefine mode(udf) abt_mode equ &17 ;abort mode(abt) sup_mode equ &13 ;supervisor mode (svc) irq_mode equ &12 ;interrupt mode (irq) fiq_mode equ &11 ;fast interrupt mode (fiq) usr_mode equ &10 ;user mode(usr) ;/*************************************************************************/ ;/* system stack memory : 8k bytes system stacks are defined at memory.a ;/*************************************************************************/ usr_stack_size equ 1024 udf_stack_size equ 512 abt_stack_size equ 512 irq_stack_size equ 2048 fiq_stack_size equ 2048 sup_stack_size equ 2048 ;/*************************************************************************/ ;/* system clock */ ;/*************************************************************************/ mhz equ 1000000 ;#ifdef ks32c50100 fmclk_mhz equ 50000000 ; 50mhz, ks32c50100 ;#else ;;fmclk_mhz equ 33000000 ; 33mhz, KS32C5000 ;fmclk_mhz equ 40000000 ; 33mhz, KS32C5000 ;#endif fmclk equ fmclk_mhz/mhz ;/*************************************************************************/ ;/* system memory control register equ tables */ ;/*************************************************************************/ ; ;/* -> extdbwth : memory bus width register */ ;------------------------------------------------------------- ;
ks32c50100/5000a risc microcontroller d iagnostic source code 3- 21 dsr0 equ 2:shl:0 ; rom0, 0 : disable ; 1 : byte ; 2 : half-word ; 3 : word dsr1 equ 2:shl:2 ; rom1 dsr2 equ 3:shl:4 ; rom2 dsr3 equ 3:shl:6 ; rom3 dsr4 equ 3:shl:8 ; rom4 dsr5 equ 3:shl:10 ; rom5 dsd0 equ 3:shl:12 ; dram0 dsd1 equ 3:shl:14 ; dram1 dsd2 equ 3:shl:16 ; dram2 dsd3 equ 3:shl:18 ; dram3 dsx0 equ 3:shl:20 ; extio0 dsx1 equ 3:shl:22 ; extio1 dsx2 equ 3:shl:24 ; extio2 dsx3 equ 3:shl:26 ; extio3 rextdbwth equ dsr0+dsr1+dsr2+dsr3+dsr4+dsr5+dsd0+dsd1+dsd2+dsd3+dsx0+dsx1+dsx2+dsx3 ;------------------------------------------------------------- ;/* -> romcon0 : rom bank0 control register */ ;------------------------------------------------------------- rombaseptr0 equ 0x000:shl:10 ;=0x0000000 romendptr0 equ 0x020:shl:20 ;=0x0200000 pmc0 equ 0x0 ; 0x0=normal rom, 0x1=4word page ; 0x2=8word page, 0x3=16word page rtpa0 equ (0x0:shl:2) ; 0x0=5cycle, 0x1=2cycle ; 0x2=3cycle, 0x3=4cycle rtacc0 equ (0x6:shl:4) ; 0x0=disable, 0x1=2cycle ; 0x2=3cycle, 0x3=4cycle ; 0x4=5cycle, 0x5=6cycle ; 0x6=7cycle, 0x7=reserved rromcon0 equ romendptr0+rombaseptr0+rtacc0+rtpa0+pmc0 ;------------------------------------------------------------- ;/* -> romcon1 : rom bank1 control register */ ;------------------------------------------------------------- some code omitted for readibility rromcon5 equ romendptr5+rombaseptr5+rtacc5+rtpa5+pmc5 ;------------------------------------------------------------- ;/* -> dramcon0 : ram bank0 control register */ ;------------------------------------------------------------- edo_mode0 equ 1 ;(edo)0=normal, 1=edo dram
diagnostic source code ks32c50100/5000a risc microcontroller 3 - 22 casprechargetime0 equ 0 ;(tcp)0=1cycle,1=2cycle casstrobetime0 equ 1 ;(tcs)0=1cycle ~ 3=4cycle dramcon0reserved equ 1 ; must be set to 1 ras2casdelay0 equ 0 ;(trc)0=1cycle,1=2cycle rasprechargetime0 equ 2 ;(trp)0=1cycle ~ 3=4clcyle drambaseptr0 equ 0x100:shl:10 ;=0x1000000 dramendptr0 equ 0x140:shl:20 ;=0x1400000 nocolumnaddr0 equ 2 ;0=8bit,1=9bit,2=10bit,3=11bits ;------------------------------------------------------------- tcs0 equ casstrobetime0:shl:1 tcp0 equ casprechargetime0:shl:3 dumy0 equ dramcon0reserved:shl:4 ; dummy cycle trc0 equ ras2casdelay0:shl:7 trp0 equ rasprechargetime0:shl:8 can0 equ nocolumnaddr0:shl:30 ; rdramcon0 equ can0+dramendptr0+drambaseptr0+trp0+trc0+tcp0+tcs0+dumy0+edo_mode0 ;---------------------------------------------------------------------------------- sras2casdelay0 equ 1 ;(trc)0=1cycle,1=2cycle srasprechargetime0 equ 3 ;(trp)0=1cycle ~ 3=4clcyle snocolumnaddr0 equ 0 ;0=8bit,1=9bit,2=10bit,3=11bits scan0 equ snocolumnaddr0:shl:30 strc0 equ sras2casdelay0:shl:7 strp0 equ srasprechargetime0:shl:8 ; rsdramcon0 equ scan0+dramendptr0+drambaseptr0+strp0+strc0 ;------------------------------------------------------------- some code omitted for readibility ;------------------------------------------------------------- rsdramcon3 equ scan3+dramendptr3+drambaseptr3+strp3+strc3 ;------------------------------------------------------------- ;/* -> refextcon : external i/o & memory refresh cycle control register */ ;------------------------------------------------------------- refcycle equ 16 ;unit [us], 1k refresh 16ms ;refcycle equ 8 ;unit [us], 1k refresh 16ms cassetuptime equ 0 ;0=1cycle, 1=2cycle casholdtime equ 0 ;0=1cycle, 1=2cycle, 2=3cycle, ;3=4cycle, 4=5cycle, refcyclevalue equ ((2048+1-(refcycle*fmclk)):shl:21) tcsr equ (cassetuptime:shl:20) ; 1cycle tcs equ (casholdtime:shl:17) extiobase equ 0x18360 ; refresh enable, vsf=1 ; rrefextcon equ refcyclevalue+tcsr+tcs+extiobase ;------------------------------------------------------------- ;srefcycle equ 16 ;unit [us], 4k refresh 64ms srefcycle equ 8 ;unit [us], 4k refresh 64ms rowcycletime equ 3 ;0=1cycle, 1=2cycle, 2=3cycle, ;3=4cycle, 4=5cycle,
ks32c50100/5000a risc microcontroller d iagnostic source code 3- 23 srefcyclevalue equ ((2048+1-(srefcycle*fmclk)):shl:21) strc equ (rowcycletime:shl:17) rsrefextcon equ srefcyclevalue+strc+extiobase ;------------------------------------------------------------- ; ;/*************************************************************************/ ;/* ks32c50100 special registers */ ;/*************************************************************************/ ; asic_base equ 0x3ff0000 ;/* interrupt control */ int_cntrl_base equ asic_base+0x4000 ;define base of all interrupt ; controller registers intmode equ asic_base+0x4000 intpend equ asic_base+0x400 4 intmask equ asic_base+0x4008 intoffset equ asic_base+0x4024 ; /* i/o port interface */ iopmod equ asic_base+0x5000 iopcon equ asic_base+0x5004 iopdata equ asic_base+0x5008 ;/* uart 0,1 */ uartlcon0 equ asic_base+0xd000 some code omitted for readibility ; /* timer 0,1 */ timer_base equ asic_base+0x6000 ;define base for all timer ; registers ;/***************************************************************/ end
diagnostic source code ks32c50100/5000a risc microcontroller 3 - 24 listing 3-12. (init.s) ;============================ ========= ; initialise memory required by c code ;===================================== import |image$$ro$$limit| ; end of rom code (=start of rom data) import |image$$rw$$base| ; base of ram to initialise import |image$$zi$$base| ; base and limit of area import |image$$zi$$limit| ; to zero initialise ldr r0, =|image$$ro$$limit| ; get pointer to rom data ldr r1, =|image$$rw$$base| ; and ram copy ldr r3, =|image$$zi$$base| ; zero init base => top of initia lised data cmp r0, r1 ; check that they are different beq %1 0 cmp r1, r3 ; copy init data ldrcc r2, [r0], #4 strcc r2, [r1], #4 bcc %0 1 ldr r1, =|image$$zi$$limit| ; top of zero init segment mov r2, #0 2 cmp r3, r1 ; zero init strcc r2, [r3], #4 bcc %2 listing 3-13. (init.s) ;==================================================== ; now change to user mode and set up user mode stack. ;==================================================== mrs r0, cpsr bic r0, r0, #lockout | mode_mask orr r1, r0, #usr_mode msr cpsr, r0 ldr sp, =usr_stack ; /* call c_entry application routine with a pointer to the first */ ; /* available memory address after ther compiler's global data */ ; /* this memory may be used by the application. */ ;=========================== ; now we enter the c program ;=========================== import c_entry bl c_entry
ks32c50100/5000a risc microcontroller d iagnostic source code 3- 25 interrupt handling exception vector address and exception handling flows are previously described in this section. ( table 3-2 , figure 3-4 ). now, the interrupt handling method of netmcu devices will be described hear. netmcu devices, KS32C5000 / 5000a /50100, have a total 21 interrupt sources. five special registers used to control the interrupt generation and handling. five special registers are as follows: interrupt mode register (intmod), interrupt mask register (intmsk), interrupt pending register (intpnd), interrupt offset register (intoffset), interrupt priority registers (intpri0,1,2,3,4,5). figure 3-4. show the isr(interrupt service routine) setup concept diagram. interrupt handling c-source codes are listed in listing 3-13. setup - initialize interrupt mode register(intmod) to fiq or irq - initialize interrupt mask register(intmsk) - clear interrupt pending register(intpnd) interrupt priority? set the interrupt priority registers (intpri0~5) to new priority values which are the index values of the interrupt sources setup interrupt service routine to interrupt vector table. ex) syssetinterrupt(index, void (*handler)()) - enable global mask bit,intmsk[20]. - enable appropriate interrupt mask bits. default change the priority done figure 3-5. setup concept diagrams for interrupt service routine
diagnostic source code ks32c50100/5000a risc microcontroller 3 - 26 listing 3-14. (isr.c) void clrintstatus(void) { intmask = 0x3fffff; // all interrupt disabled include global bit intpend = 0x1fffff; // all clear pending intmode = 0x1fffff; // all fiq mode /* * interrupt priority reset value. need to be changed priority, * set interrupt priority register. in this case, global interrupt * mask bit must be disabled. * */ #ifdef int_priority intpri0 = 0x03020100; intpri1 = 0x07060504; intpri2 = 0x0b0a0908; intpri3 = 0x0f0e0d0c; intpri4 = 0x13121110; intpri5 = 0x00000014; intoffset = read only register #endif } /******************************************/ /**** exception handler function ****/ /******************************************/ void isr_undefhandler(reg32 *adr) { //print("\n** trap : undefined handler\n") ; print("\rundefined address : %08x ",adr); print("\rundefined data : %08x ",*adr); } void isr_prefetchhandler(reg32 *adr) { //print("\n** trap : prefetch abort handler\n") ; print("\rprefetch abort address : %08x ",adr); print("\rprefetch abort data : %08x ",*adr); } void isr_aborthandler(reg32 *adr) { //print("\n** trap : data abort handler\n") ; print("\rdata abort address : %08x ",adr); print("\rdata abort data : %08x ",*adr); } void isr_swihandler(void) {
ks32c50100/5000a risc microcontroller d iagnostic source code 3- 27 print("\r** trap : swi handler\n") ; } void isr_irqhandler(void) { intoffset = (u32)intoffset; clear_pendingbit(intoffset>>2) ; (*interrupthandlers[intoffset>>2])(); // call interrupt service routine } void isr_fiqhandler(void) { intoffset = (u32)intoffset; clear_pendingbit(intoffset>>2) ; (*interrupthandlers[intoffset>>2])(); // call interrupt service routine } /***********************************************************************/ /* initinthandlertable: initialize the interrupt handler table */ /* note(s): this should be called during system initialization */ /***********************************************************************/ void initinthandlertable(void) { reg32 i; for (i = 0; i < maxhndlrs; i++) interrupthandlers[i] = dummyisr; } /*********************************************************/ /* syssetinterrupt: setup interrupt handler vector table */ /*********************************************************/ void syssetinterrupt(reg32 vector, void (*handler)()) { interrupthandlers[vector] = handler; } /*********************************************************/ /* initinterrupt: initialize interrupt */ /*********************************************************/ void initinterrupt(void) { clrintstatus(); // clear all interrupt in itinthandlertable() ; }
diagnostic source code ks32c50100/5000a risc microcontroller 3 - 28 the interrupt offset register [intoffset] is a special function of the netmcu device that solves the interrupt latency problem caused by many interrupt resources. intoffset has the index value of the top priority interrupt which already is enabled by the interrupt mask bit[intmsk] and is pending on the interrupt pending register [intpnd]. therefore, the appropriate interrupt service routine in interrupt vector table which is defined as function array can be serviced by reference the value of intoffset. for examples, void isr_irqhandler(void) { intoffset = (u32)intoffset; clear_pendingbit(intoffset>>2) ; (*interrupthandlers[intoffset>>2])(); // call interrupt service routine } interrupt pending bit also cleared in this interrupt handler. an example of the interrupt handling process figure 3-6 shows the irq interrupt handling process. for the more easy understand about interrupt handling process, i am going to explain the irq interrupt handling process as an example. upon the arm7 series architecture, the exception vector table is on the address 0x0 to 0x1c. so boot rom have to be located at address zero. after the power on reset or reset signal input, boot rom exception vector table is mirrored to dram exception vector tables using default exception handler. for example, the irq interrupt vector address,0x18, has the address of irq_handler. using this default handler, irq vector table mirrored to dram irq handler vector table. the irq handler vector table on dram will be initialized by systemirqhandler during the boot processing. systemirqhandler will call the c-coded irq handler, isr_irqhandler() when the irq interrupt occurred. dram memory map is difined at memory.a (listing 3-13) .
ks32c50100/5000a risc microcontroller d iagnostic source code 3- 29 reset_handler undefined_handler swi_handler prefetch_handler abort_handler reserved irq_handler fiq_handler 0x0 0x4 0x8 0xc 0x10 0x14 0x18 0x1c irq_handler sub sp, sp, #4 stmfd sp!, {r0} ldr r0, =handleirq ldr r0, [r0] str r0, [sp, #4] ldmfd sp!, {r0, pc} usercodearea systemundefinedhandler systemswihandler systemprefetchhandler systemaborthandler systemreserv systemirqhandler systemfiqhandler =handlereset ~ void isr_irqhandler(void) { intoffset=(u32)intoffset; clear_pendingbit(intoffset>>2) ; (*interrupthandlers[intoffset>>2])(); } ~ systemirqhandler import isr_irqh andler stmfd sp!, {r0- r12, lr} bl isr_irqhandler ldmfd sp!, {r0-r12, lr} subs pc, lr, #4 =usercodearea =handleundef =handleswi =handleprefetch =handleabort =handleirq =handlefiq stack area user area boot rom dram sp_irq mirrored by boot processing figure 3-6. example of irq interrupt handling process
diagnostic source code ks32c50100/5000a risc microcontroller 3 - 30 time interrupt request runing code user isr code - copies cpsr into spsr - set the appropriate cpsr mode bits: > to change to the appropriate mode > to disable interrupts. - stores the return address - sets the pc to the appropriate vector address cpu context saved isr entry function - branch the mirrored vector table on dram and jump to the function call handler - stores all the working registers and link register - call c- interrupt handler isr exit function - restores the saved working registers and link registers - set pc to return address interrupt latency interrupt response interrupt recoveries figure 3-7. interrupt latency, response and recoveries of netmcu device
ks32c50100/5000a risc microcontroller d iagnostic source code 3- 31 interrupt latency, interrupt response and recoveries the worst case latency for fiq, assuming that it is enabled, consists of the longest time the request can take to pass through the synchronizer( tsyncmax if asynchronous), plus the time for the longest instruction to complete ( tldm ,the longest instruction is an ldm which loads all the registers including pc), plus the time for the data abort entry ( texe ), plus the time for fiq entry ( tfig ). at the end of this time arm7tdmi will be executing the instruction at 0x1c. tsyncmax is 3 processor cycles, tldm is 20 cycles, texe is 3 cycles, and tfiq is 2 cycles. the total time is therefore 28 processor cycles. interrupt latency = tsyncmax (3cycles) + tldm (20cycles) + texe (3cycles) + tfiq (2cycles) = 28 cycles. the maximum irq latency calculation is similar, but must allow for the fact that fiq has higher priority and could delay entry into the irq handling routine for an arbitrary length of time. the minimum latency for fiq or irq consists of the shortest time the request can take through the synchronizer( tsyncmin ), plus tfiq . this is 4 processor cycles. instruction & data cache / internal sram the netmcu devices has the unified(instruction / data) cache. this cache memory can be configured to internal sram using system configuration register[syscfg]. listing 3-15, the c source code demonstrate the usage of cache memory. it can be configured as 4k cache/4k sram or all cache or sram depending on the set values of the syscfg register. listing 3-15. (system.c) void syscfginit(int cm) { /* disable cache before cache mode change */ syscfg &= ~(stall|cache|cache_mode|write_buff); switch(cm) { case 0 : /* 4k cache,4k sram */ syscfg |=(cache_mode_00|write_buff); cacheflush(); syscfg |=cache; /* cache enable */ break; case 1 : /* 8k cache */ syscfg |=(cache_mode_01|write_buff); cacheflush(); syscfg |=cache; /* cache enable */ break; case 2 : /* cache off: 8k sram */ syscfg |=(cache_mode_10|write_buff); cacheflush(); default : break; }
diagnostic source code ks32c50100/5000a risc microcontroller 3 - 32 cache flush operation if you change the cache mode or memory map configurations when the cache is enabled, then memory consistency problem will be occurred. so, in advance that, you have to clear the tag ram for flush the cache. listing 3-16. (system.c) /* * cache flush function for re-configuration cache mode * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ */ void cacheflush(void) { int i; unsigned int *tagram; tagram = (unsigned int *)tagram; syscfg &= ~cache; // disable cache before cache flush for(i=0; i < 256; i++) { *tagram = 0x00000000; // clear tag ram tagram += 1; } //print("\ncache flushed!!\r"); }
ks32c50100/5000a risc microcontroller d iagnostic source code 3- 33 iic bus controller the netmcu device ? s iic bus controller supports only single master mode. the 64k iic serial eeprom, ks24l321/641, is used as the slave device for the usage of netmcu device ? s iic interface. for the purpose of more understanding about iic serial interface protocol, i am about to introduce the function description of the ks24l321/641. this iic serial eeprom used as the storage of the target system configuration parameters like as uart baud rate, mac address, iic serial prescaler clock etc. functional descriptions of ks24l321/641 i 2 c-bus interface the ks24l321/641 supports the i 2 c-bus serial interface data transmission protocol. the two-wire bus consists of a serial data line (sda) and a serial clock line (scl). the sda and the scl lines must be connected to v cc by a pull-up resistor that is located somewhere on the bus. any device that puts data onto the bus is defined as a ? transmitter ? and any device that gets data from the bus is a ? receiver. ? the bus is controlled by a master device which generates the serial clock and start/stop conditions, controlling bus access. using the a0, a1, and a2 input pins, up to eight ks24l321/641 devices can be connected to the same i 2 c-bus as slaves (see figure 3-8). both the master and slaves can operate as a transmitter or a receiver, but the master device determines which bus operating mode would be active ks24l321/641 tx/rx a0 a1 a2 r r netmcu slave1 ks24l321/641 tx/rx a0 a1 a2 ks24l321/641 tx/rx a0 a1 a2 ks24l321/641 tx/rx a0 a1 a2 slave2 slave3 slave8 sda scl vcc vcc to vcc or vss to vcc or vss to vcc or vss to vcc or vss bus master receiver) (trasnmitter/ figure 3-8. typical configuration
diagnostic source code ks32c50100/5000a risc microcontroller 3 - 34 i 2 c-bus protocols here are several rules for i 2 c-bus transfers: ? a new data transfer can be initiated only when the bus is currently not busy. ? msb is always transferred first in transmitting data. ? during a data transfer, the data line (sda) must remain stable whenever the clock line (scl) is high. the i 2 c-bus interface supports the following communication protocols: ? bus not busy : the sda and the scl lines remain in high level when the bus is not active. ? start condition : a start condition is initiated by a high-to-low transition of the sda line while scl remains in high level. all bus commands must be preceded by a start condition. ? stop condition : a stop condition is initiated by a low-to-high transition of the sda line while scl remains in high level. all bus operations must be completed by a stop condition (see figure 3-9). scl sda start condition data/ack valid data change stop condition figure 3-9. data transmission sequence ? data valid: following a start condition, the data becomes valid if the data line remains stable for the duration of the high period of scl. new data must be put onto the bus while scl is low. bus timing is one clock pulse per data bit. the number of data bytes to be transferred is determined by the master device. the total number of bytes that can be transferred in one operation is theoretically unlimited. ? ack (acknowledge): an ack signal indicates that a data transfer is completed successfully. the transmitter (the master or the slave) releases the bus after transmitting eight bits. during the 9th clock, which the master generates, the receiver pulls the sda line low to acknowledge that it has successfully received the eight bits of data (see figure 3-10). but the slave does not send an ack if an internal write cycle is still in progress. in data read operations, the slave releases the sda line after transmitting 8 bits of data and then monitors the line for an ack signal during the 9th clock period. if an ack is detected but no stop condition, the slave will continue to transmit data. if an ack is not detected, the slave terminates data transmission and waits for a stop condition to be issued by the master before returning to its stand-by mode.
ks32c50100/5000a risc microcontroller d iagnostic source code 3- 35 master scl line data from transmitter ack from receiver bit1 bit9 ack figure 3-10. acknowledge response from receiver ? slave address : after the master initiates a start condition, it must output the address of the device to be accessed. the most significant four bits of the slave address are called the ? device identifier. ? the identifier for the ks24l321/641 is ? 1010b ? . the next three bits comprise the address of a specific device. the device address is defined by the state of the a0, a1, and a2 pins. using this addressing scheme, you can cascade up to eight ks24l321/641s on the bus (see figure 3-11 below). ? read/write : the final (eighth) bit of the slave address defines the type of operation to be performed. if the r / w bit is ? 1 ? , a read operation is executed. if it is ? 0 ? , a write operation is executed 1 0 1 0 a2 a1 a0 r/w device identifier device select x x x a12 a11 a10 a9 a8 first(high) address slave address first word address a7 a6 a5 a4 a3 a2 a1 a0 second(low) address second word address notes: 1. the a12 is "don`t care " for the ks24l321 2. x means "don`t care" figure 3-11. device address
diagnostic source code ks32c50100/5000a risc microcontroller 3 - 36 initialize the iic bus controller before the use of iic bus controller, iic control status register[iiccon] and iic prescaler register[iicps] have to be initialized. listing 3-17 shows the iic initialize c-routine. where, the iic prescaler frequency,fscl is defined at sysconf.h which is the snds100 target system configuration header file. listing 3-17. (iic.c) /****************************************************************** * * * iic setup routine * * * ******************************************************************/ void iicsetup(void) { // reset iic controller iiccon = iicreset ; // set prescale value: fscl is iic serial clock frequency // fscl defined at sysconf.h iicps = setprescaler((int)fscl); //support upto 100khz } /****************************************************************** * * * setup iic prescaler value from serial clock frequency * * * ******************************************************************/ int setprescaler(int sclk) { return((int)(((fmclk/sclk)-3.0)/16.0)-0.5); //add 0.5 for }
ks32c50100/5000a risc microcontroller d iagnostic source code 3- 37 iic write c-function library the ks24c321/641 writes up to 32-bytes of data(=page size). a page write operation is initiated in the same way as byte write operation. however, instead of finishing the write operation after the first data byte is transferred, the master can transmit up to 31 additional bytes. the ks24l321/641 responds with an ack each time it receives a complete byte of data (see figure 3-12 ). start slave address first word address second word address data byte 0 data byte n (n <= 31) stop a c k a c k a c k a c k a c k a c k figure 3-12. page write operation the ks24l321/641 automatically increments the word address pointer each time it receives a complete data byte. when one byte is received, the internal word address pointer increments to the next address so that the next data byte can be received. if the master transmits more than 32 bytes before it generates a stop condition to end the page write operation, the ks24l321/641 word address pointer value ? rolls over ? and the previously received data is overwritten. if the master transmits less than 32 bytes and generates a stop condition, the ks24l321/641 writes the received data to the corresponding eeprom address. during a page write operation, all inputs are disabled and there would be no response to additional requests from the master until the internal write cycle is completed. you can writes data to a slave(iic serial eeprom) using the iic write library functions(listing 3-18). this write function divide the transfer data to page size and transmit it to slave until all transfer data is sent. netmcu device ? s iic bus controller has the only one interrupt source for iic. so, whenever the write operation or read operation is started, iic interrupt service routine have to be installed at vector table using syssetinterrupt(). the data structure for iic read & write library function is difined at iic header file( iic.h ).
diagnostic source code ks32c50100/5000a risc microcontroller 3 - 38 listing 3-18. (iic.c) /****************************************************************** * * * library functions for iic read & write * * ks24c32/64 : iic serial eeprom * * * ******************************************************************/ void iicwriteint(u8 slaveaddr,u32 writeaddr,u8 *data,u32 sizeofdata) { int page,j; int no_of_page; /* number of page */ int remain_byte; u32 pageaccessaddr; syssetinterrupt(niic_int,iicwriteisr) ; /*setup iic tx interrupt */ enable_int(niic_int) ; pageaccessaddr = writeaddr; iic_txmit.slave_addr = slaveaddr; no_of_page = (int)(ceil(sizeofdata/(u32)sizeofpage)); remain_byte = (int)(sizeofdata%(u32)sizeofpage); for(page=0; page <= no_of_page;page++) { if(sizeofdata < sizeofpage) for(j=0; j < sizeofdata; j++) iic_txmit.page_buffer[j] = *data++; iic_txmit.writedatasize = sizeofdata; } else { if(page == no_of_page) { for(j=0; j < remain_byte; j++) iic_txmit.page_buffer[j] = *data++; iic_txmit.writedatasize = remain_byte; } else { for(j=0; j < sizeofpage; j++) iic_txmit.page_buffer[j] = *data++; iic_txmit.writedatasize = sizeofpage; } } iicsetup(); iic_txmit.flag = 0x0; iic_txmit.buffbytecnt = 0x0; iic_txmit.byte_addr_msb = (u8)((pageaccessaddr>>8) & 0xff); iic_txmit.byte_addr_lsb = (u8)(pageaccessaddr & 0xff);
ks32c50100/5000a risc microcontroller d iagnostic source code 3- 39 /* step 1: setup iicon register for transmit start */ while(iiccon & busy); /* wait! the iic bus is busy */ iiccon = start|ack|ien; /* now, start to transmit */ /* send slave address and write command */ iicbuf = iic_txmit.slave_addr|s_write; while(!(iic_txmit.flag & iic_page_tx_done)); pageaccessaddr += sizeofpage; for(j=0; j< (int)write_cycle_ms(5); j++); /* for 5ms write cycle */ } } /****************************************************************** * * * iic interrupt service routines * * * ******************************************************************/ void iicwriteisr(void) { if(!(iic_txmit.flag & (u32)iic_byte_addr_msb)) /* send byte address: msb */ iicbuf = iic_txmit.byte_addr_msb; iic_txmit.flag |= (u32)iic_byte_addr_msb; } else if(!(iic_txmit.flag & (u32)iic_byte_addr_lsb)) { /* send byte address: lsb */ iicbuf = iic_txmit.byte_addr_lsb; iic_txmit.flag |= (u32)iic_byte_addr_lsb; } else if(iic_txmit.buffbytecnt < iic_txmit.writedatasize) { iicbuf = iic_txmit.page_buffer[iic_txmit.buffbytecnt++]; } else /* stop iic controller */ iiccon = stop; /* byte data or page data transmit done */ iic_txmit.flag |= (u32)iic_page_tx_done; } }
diagnostic source code ks32c50100/5000a risc microcontroller 3 - 40 iic read c-function library iic read c library function, iicreadint(), were implemented by using the following random read byte and sequential read operation. random address byte read operation using random read operations, the master can access any memory location at any time. before it issues the slave address with the r / w bit set to ? 1 ? , the master must first perform a ? dummy ? write operation. this operation is performed in the following steps: 1. the master first issues a start condition, the slave address, and the word address (the first and the second addresses) to be read. (this step sets the internal word address pointer of the ks24l321/641 to the desired address.) 2. when the master receives an ack for the word address, it immediately re-issues a start condition followed by another slave address, with the r / w bit set to ? 1 ? . 3. the ks24l321/641 then sends an ack and the 8-bit data stored at the pointed address. 4. at this point, the master does not acknowledge the transmission, generating a stop condition. 5. the ks24l321/641 stops transmitting data and reverts to stand-by mode (see figure 3-13). start slave address first word address second word address data byte stop a c k a c k a c k a c k n o a c k start slave address figure 3-13. random address byte read operation
ks32c50100/5000a risc microcontroller d iagnostic source code 3- 41 sequential read operation sequential read operations can be performed in two ways: current address sequential read operation, and random address sequential read operation. the first data is sent in either of the two ways, current address byte read operation or random address byte read operation described earlier. if the master responds with an ack, the ks24l321/641 continues transmitting data. if the master does not issue an ack, generating a stop condition, the slave stops transmission, ending the sequential read operation. using this method, data is output sequentially from address ? n ? followed by address ? n+1 ? . the word address pointer for read operations increments to all word addresses, allowing the entire eeprom to be read sequentially in a single operation. after the entire eeprom is read, the word address pointer ? rolls over ? and the ks24l321/641 continues to transmit data for each ack it receives from the master (see figure 3-14). stop a c k n o a c k start slave address data byte(n) data byte(n+1) a c k data byte(n+x) a c k a c k ~ ~ figure 3-14. sequential read operation
diagnostic source code ks32c50100/5000a risc microcontroller 3 - 42 listing 3-19. (iic.c) void *iicreadint(u8 slaveaddr,u32 readaddr,u32 sizeofdata) { u8 *readptr; /* data read pointer */ iicsetup(); syssetinterrupt(niic_int,iicreadisr) ; /*setup iic tx interrupt */ enable_int(niic_int) ; /*memory alloc for receive data */ if((readptr = (u8 *)malloc((unsigned)sizeofdata)) == (u8 *)(null)) print("\rmemory allocation error occurred!!!\r"); iic_recv.rcv_buffer = readptr; iic_recv.flag = 0x0; iic_recv.bytereadcnt = 0x0; iic_recv.readdatasize = sizeofdata; iic_recv.slave_addr = slaveaddr; iic_recv.byte_addr_msb = (u8)((readaddr>>8) & 0xff); iic_recv.byte_addr_lsb = (u8)(readaddr & 0xff); /* step 1: setup iicon register for receive start */ while(iiccon & busy); /* wait! the iic bus is busy */ iiccon = start|ack|ien; /* send slave address and write command */ iicbuf = iic_recv.slave_addr|s_write; while(!(iic_recv.flag & iic_byte_rx_done)); return(readptr); /* return receive data pointer */ } void iicreadisr(void) { if(!(iic_recv.flag & (u32)iic_byte_addr_msb)) //else if(!(iic_recv.flag & (u32)iic_byte_addr_msb)) /* send byte address: msb */ iicbuf = iic_recv.byte_addr_msb; iic_recv.flag |= (u32)iic_byte_addr_msb; /* send msb byte addr */ } else if(!(iic_recv.flag & (u32)iic_byte_addr_lsb)) { /* send byte address: lsb */ iicbuf = iic_recv.byte_addr_lsb; iic_recv.flag |= (u32)iic_byte_addr_lsb; /* send lsb byte addr */ } else if(!(iic_recv.flag & (u32)iic_repeat_start)) { /* repeat start */ iiccon = restart; iiccon = start|ack|ien; iicbuf = iic_recv.slave_addr|s_read; iic_recv.flag |= (u32)iic_repeat_start;
ks32c50100/5000a risc microcontroller d iagnostic source code 3- 43 } else if(!(iic_recv.flag & (u32)iic_multi_recv)) { /* receive multiple data */ iiccon = ack|ien; iic_recv.flag |= (u32)iic_multi_recv; } else if(iic_recv.bytereadcnt < iic_recv.readdatasize-1) { *(iic_recv.rcv_buffer)++ = iicbuf; iic_recv.bytereadcnt++; } else if(!(iic_recv.flag & (u32)iic_no_more_recv)) /* now,no more received data is required from slave */ iiccon = noack|ien; iic_recv.flag |= (u32)iic_no_more_recv; } else { /* receive last data and stop */ *(iic_recv.rcv_buffer)++ = iicbuf; /* stop iic controller */ iiccon = stop; /* byte data receive done */ iic_recv.flag |= (u32)iic_byte_rx_done; } }
diagnostic source code ks32c50100/5000a risc microcontroller 3 - 44 uart (universal asyncronous receiver/transmitter) the KS32C5000(a)/50100 uart unit provides two channel serial communication ports. this uart unit were implemented and embedded as console port. so, it did not support full modem interface pins. it only support that four serial input or output pins which are the data transmit and receive pins(uatxd/uarxd) ,data set ready (nuadsr), data terminal ready(nuadtr) pin per channel. if you needs the full modem interface pins, you can implement it use by general i/o ports or you have to use an commercial uart chip which will be described on the next section in this application notes. the KS32C5000(a) uart features almost same as the ks32c50100 except it have 16bytes receive fifo and one more interrupt source for receive error. (see user ? s manual for more details). but the listed uart driver sources can be used for the KS32C5000(a) and ks32c50100 commonly. uart baud rate you can choose the external clock or internal system clock as uart clock source to generate an appropriate baud rate. for the external uart clock, 29.4912mhz oscillator is mounted on snds100 rev1.0 target board. if you are using KS32C5000 device, you have to choose internal system clock for uart because it did not support external uart input pin. program tips for buad rate calculation (buad50100.zip for ks32c50100, buad5k.zip for KS32C5000(a)) are available at our web site. the following baud rate tables are obtained from this program tips. table 3-2. baud rate table for ks32c50100 (fmclk = 25mhz) ubrdivn typical[bps] spec.[bps] error rate[%] 0x5150 1200.1 1200 0.006 0x28a0 2400.2 2400 0.006 0x1450 4792.9 4800 -0.147 0x0a20 9585.9 9600 -0.147 0x0500 19290.1 19200 0.469 0x0280 38109.8 38400 -0.756 0x01a0 57870.4 57600 0.469 0x00d0 111607.1 115200 -3.119 0x0060 223214.3 230400 -3.119
ks32c50100/5000a risc microcontroller d iagnostic source code 3- 45 table 3-3. baud rate table for KS32C5000(a) (fmclk = 33mhz) ubrdivn typical[bps] spec.[bps] error rate[%] 0x000d6 9593.0 9600 -0.073 0x0006b 19097.2 19200 -0.535 0x0006a 19275.7 19200 0.394 0x00035 38194.4 38400 -0.535 0x00023 57291.7 57600 -0.535 0x00011 114583.3 115200 -0.535 0x00008 229166.7 230400 -0.535 table 3-4. baud rate table for KS32C5000(a)/50100 (fmclk = 29.4912mhz) ubrdivn typical[bps] spec.[bps] error rate[%] 0x0bf0 9600.0 9600 0.000 0x05f0 19200.0 19200 0.000 0x02f0 38400.0 38400 0.000 0x01f0 57600.0 57600 0.000 0x00f0 115200.0 115200 0.000 0x0070 230400.0 230400 0.000 0x0030 460800.0 460860 0.013 0x0010 921600.0 921600 0.000 to initialize the uart baud rate divisor register[ubrdivn], the following data structure used to reference the ubrdivn register initialize value according to be given baud rate. typedef struct { uint32 baud; /* baud rate: ex) 115200bps */ uint32 div; /* divisor register value for given baud rate */ }baudtable; you can get the divisor register setting value from baudrateval(uint32 baud) function. this function return the index value of baud rate table for be given uart baud rate. for example: rbrdivn = u_baudrate[baudrateval(115200)].div; if you select the external uart clock(29.4912mhz), the baud rate divisor value, 0x0000f, can be get after the above statement is run.
diagnostic source code ks32c50100/5000a risc microcontroller 3 - 46 listing 3-20. (uart.c) baudtable u_baudrate[baud_table] = { #ifdef ex_uclk /* for 29.4912mhz uart clock */ 9600, 0x000bf, 19200, 0x0005f, 38400, 0x0002f, 57600, 0x0001f, 115200, 0x0000f, 230400, 0x00007, 460800, 0x00003 #else #ifdef ks32c50100 /* for 50mhz/2 uart clock */ 9600, 0x00a20, 19200, 0x00500, 38400, 0x00280, 57600, 0x001a0, 115200, 0x000d0, 230400, 0x00060, 460800, 0x00020 // not available #else /* for 33mhz uart clock */ 9600, 0x000d6, 19200, 0x0006a, 38400, 0x00035, 57600, 0x00023, 115200, 0x00011, 230400, 0x00008, 460800, 0x00008 // not available #endif #endif }; uint32 baudrateval(uint32 baud) { uint32 index; for(index = 0; index < baud_table; index++) { if(u_baudrate[index].baud == baud) return(index); } return(0); /* baudrate data doesn't in table */ }
ks32c50100/5000a risc microcontroller d iagnostic source code 3- 47 uart initializations all data structures for uart configuration and initialization are defined at uart c-header file.( uart.h ) listing 3-20. (uart.c) uint32 uart_initialize() { disable_int(nglobal_int); /* global interrupt disabled */ /*****************************/ /* initialize uart channel 0 */ /*****************************/ uart_dev_init.com_port = serial_dev0; /* com 0 */ uart_dev_init.baud_rate = baudrate; uart_dev_init.data_mode = (ucon_rxm_intreq|ucon_txm_intreq|ucon_rxstat_int); uart_dev_init.parity = ulcon_pmd_no; /* no parity */ uart_dev_init.stop_bits = 0; /* one bit */ uart_dev_init.data_bits = ulcon_wl8; /* 8bits */ #ifdef ex_uclk uart_dev_init.clk_sel = ulcon_uclk; /* external clock,29.4912mhz */ #else uart_dev_init.clk_sel = 0; /* internal clock */ #endif uart_init(&uart_dev_init); /*****************************/ /* initialize uart channel 1 */ /*****************************/ uart_dev_init.com_port = serial_dev1; /* com 0 */ uart_init(&uart_dev_init); enable_int(nglobal_int); /* global interrupt disabled */ return(success); } /***************************/ /* uart main init function */ /***************************/ uint32 uart_init(serial_dev *s) { uint32 ruartbrd; /* uart interrupt off */ uartrxintoff(s->com_port); uarttxintoff(s->com_port); /* initialize uart transmit & receive queue */ txqinit(s->com_port); rxqinit(s->com_port);
diagnostic source code ks32c50100/5000a risc microcontroller 3 - 48 /* default baud rate will be set. sysconf.h */ ruartbrd = u_baudrate[baudrateval(s->baud_rate)].div; if(s->com_port) { /* interrupt service routine setup */ syssetinterrupt(nuart1_tx_int, uart1txlisr); #ifdef ks32c50100 syssetinterrupt(nuart1_rx_err_int, uart1rxerrlisr); #else syssetinterrupt(nuart1_rx_int, uart1rxerrlisr); syssetinterrupt(nuart1_error_int, uart1rxerrlisr); #endif uartlcon1 = s->data_bits|s->stop_bits|s->parity|s->clk_sel; uartcont1 = s->data_mode; uartbrd1 = ruartbrd; } else { /* interrupt service routine setup */ syssetinterrupt(nuart0_tx_int, uart0txlisr); #ifdef ks32c50100 syssetinterrupt(nuart0_rx_err_int, uart0rxerrlisr); #else syssetinterrupt(nuart0_rx_int, uart0rxerrlisr); syssetinterrupt(nuart0_error_int, uart0rxerrlisr); #endif /* uart mode, default baud rate setup */ uartlcon0 = s->data_bits|s->stop_bits|s->parity|s->clk_sel; uartcont0 = s->data_mode; uartbrd0 = ruartbrd; } //uartrxinton(s->com_port); //uarttxinton(s->com_port); return(success); }
ks32c50100/5000a risc microcontroller d iagnostic source code 3- 49 uart polled i/o functions put_char() and get_char() is implemented for to transmit and receive data through uart channel in polling method. these poll function check the uart buffer status using by uart status register[ustatn] for data transfer. if the uart transmit holding register[uarttxhn] is in empty state, then the byte data will be written to it. uarttxhn register ? s data will be shifted out from transmit shift register to uart transmit output pin[uatxdn] serially. if the uart receive buffer register[urxbufn] is filled with received data, the get_char() will return the byte data of uexbufn. the formatted output polled i/o function, print() is defined at pollio.c. this function is similar to printf(), ansi c standard library function. listing 3-21. (uart.c) void put_char(uint32 channel,char ch) { if(channel) { waitxmitter(uartstat1); uarttxh1 = ch; } else { waitxmitter(uartstat0); uarttxh0 = ch; } } char get_char(uint32 channel) { char ch; if(channel) { waitrcver(uartstat1); ch = uartrxb1; } else { waitrcver(uartstat0); ch = uartrxb0; } return ch; } void put_string(char *ptr ) { while(*ptr ) { put_byte(*ptr++ ); } }
diagnostic source code ks32c50100/5000a risc microcontroller 3 - 50 the circular queue to transfer the uart data by interrupt method, the circular queue used for uart data structure as following: /* transmit & receive que data structure */ #define maxevent 10 /* 10 bytes buffer */ typedef struct { char buff[maxevent]; /* data buffer */ int wptr; /* write pointer */ int rptr; /* read pointer */ } uart_buffer; to create a circular queue for use in uart i/o functions based on the interrupt method, the function txqwr() for transmit data write queue and rxqrd() for receive data read queue and uart interrupt service routines for transmit/receive data from queue.(listing 3-22) the uart interrupt service routines for data transferring are already registered at interrupt vector table at uart initialize function ,uart_initialize(), is called. (listing 3-20). if the uart tx/rx interrupt were enabled and an event occurred for rx or tx, then the uart interrupt service routines,uart0txlisr()/uart0rxlisr() for channel 0, will be served. listing 3-22. (uart.c) /* transmit que write function */ uint32 txqwr(uint32 channel,uint8 data) { if(txq[channel].wptr+1 == txq[channel].rptr) { return(error); /* ring buffer full state */ } txq[channel].buff[txq[channel].wptr++] = data; if(txq[channel].wptr == maxevent) { txq[channel].wptr=0; } return(success); } /* receive que read function */ uint8 rxqrd(uint32 channel) { if(rxq[channel].rptr == maxevent) rxq[channel].rptr=0; /*loop back*/ if(rxq[channel].rptr == rxq[channel].wptr) return('\0');
ks32c50100/5000a risc microcontroller d iagnostic source code 3- 51 return(rxq[channel].buff[rxq[channel].rptr++]); } void uart0txlisr(void) { if(uartstat0 & ustat_txb_empty) { if(txq[0].rptr == maxevent) txq[0].rptr=0; /*loop back*/ if(txq[0].rptr != txq[0].wptr) { uarttxh0 = txq[0].buff[txq[0].rptr++]; } } uarttxintoff(0); } /* rcv, error interrupt service routine */ void uart0rxerrlisr(void) { if(!(uartstat0 & ustat_error)) { if(rxq[0].wptr+1 != rxq[0].rptr) { rxq[0].buff[rxq[0].wptr++] = uartrxb0; if(rxq[0].wptr == maxevent) rxq[0].wptr = 0; /*loop back*/ } } uartrxintoff(0); } the uart transmit interrupt is transmit done interrupt. so, transmitting one byte data to uart channel by interrupt mode, uart tx interrupt test pending bit have to be set forcing to generate tx interrupt. (see uarttxinton() ,listing 3-23). the transmit queue data will be written to uart holding register[uarttxhn] whenever the tx interrupt occurred. after the written data all shifted out to uart channel, uart transmit done interrupt will be occurred. if the uart tx interrupt switched to on/off repeatedly for data transfer in poll or interrupt mode, that means tx interrupt occurred two times per each byte data. it ? s caused to increase the interrupt response times. as a results, the cpu performance also can be degraded. to avoid this situation, you have to clear the pending register at the end of the transmit interrupt service routine. as clear the pending register which is set by transmit done interrupt, the transmit done interrupt can not served. actually, this transmit done is useless and dummy interrupt. (listing 3-23).
diagnostic source code ks32c50100/5000a risc microcontroller 3 - 52 where, the setpendingbit() is a macro function defined at interrupt handler c-code header file. ( isr.h ). using this macro function, the uart transmit interrupt pending bit of interrupt pending test register[intpndtst] according to the argument value of setpendingbit() can be set. listing 3-23. (uart.c) void uarttxinton(uint32 channel) { if(channel) { /* enable interrupt */ enable_int(nuart1_tx_int); setpendingbit(nuart1_tx_int); } else { /* enable interrupt */ enable_int(nuart0_tx_int); setpen dingbit(nuart0_tx_int); } } void uartrxinton(uint32 channel) { if(channel) { /* enable interrupt */ #ifdef ks32c50100 /* ks32c50100 */ enable_int(nuart1_rx_err_int); #else /* KS32C5000 */ enable_int(nuart1_rx_int); enable_int(nuart1_error_int); #endif } else { /* enable interrupt */ #ifdef ks32c50100 /* ks32c50100 */ enable_int(nuart0_rx_err_int); #else /* KS32C5000 */ enable_int(nuart0_rx_int); enable_int(nuart0_error_int); #endif } } void uarttxintoff(uint32 channel) { if(channel) { /* enable interrupt */ disable_int(nuart1_tx_int); clear_pendingbit(nuart1_tx_int) ;
ks32c50100/5000a risc microcontroller d iagnostic source code 3- 53 } else { /* disable interrupt */ disable_int(nuart0_tx_int); clear_pendingbit(nuart0_tx_int) ; } } void uartrxintoff(uint32 channel) { if(channel) { /* disable interrupt */ #ifdef ks32c50100 /* ks32c50100 */ disable_int(nuart1_rx_err_int); #else /* KS32C5000 */ disable_int(nuart1_rx_int); disable_int(nuart1_error_int); #endif } else { /* disable interrupt */ #ifdef ks32c50100 /* ks32c50100 */ disable_int(nuart0_rx_err_int); #else /* KS32C5000 */ disable_int(nuart0_rx_int); disable_int(nuart0_error_int); #endif } }
diagnostic source code ks32c50100/5000a risc microcontroller 3 - 54 uart interrupted i/o functions you can get an input character from uart channel using by get character function,i_getc(channel). (listing 3-24). whenever the i_getc() is called, the receive interrupt enabled by uartrxinton() and the receive data queue,rxqrd(), is accessed. the rx queue will be updated to the received new data in the rx interrupt service routine(isr). receive interrupt will be disabled at the end of the rx isr. listing 3-24. (uart.c) uint8 i_getc(uint32 channel) { uartrxinton(channel); /* receive interrupt on */ return(rxqrd(channel)); /* read receive que, if there is no data in rxq, null will be returned */ } /* interrupt get string */ uint32 i_gets(uint32 channel, uint8 *s) { uint32 count; uint8 c; count = 0; while((c = (uint8)i_getc(channel)) != cr) { count++; *s++ = c; } *s = (uint8)null; return(count); } for the one byte data transfer to an channel by interrupt method, i_putc() is implemented as follows: (listing 3-25) the first, transmit complete(tc) bit of uart status register will be checked to confirm the former data all shifted out to channel. the second, transmit interrupt will be enabled when the byte data is written to transmit queue successfully. the byte data in transmit queue will be sent to be given channel in uart transmit interrupt service routine.
ks32c50100/5000a risc microcontroller d iagnostic source code 3- 55 listing 3-25. (uart.c) uint32 i_putc(uint32 channel, uint8 ch) { if(u_tx_complete(channel)) /* check transmit complet */ { if(txqwr(channel, ch)) /* write data to tx que */ { uarttxinton(channel); /* transmit interrupt on */ while(!u_buff_empty(channel)); /* wait for tx buffer empty */ return(success); } } return(error); } /* uart interrupt put string */ uint32 i_puts(uint32 channel, uint8 *str) { uint32 i; /* working variable */ uint32 sz; sz = strlen((const char *)str); /* loop to print out all characters. */ for(i=0; i < sz ; i++) { /* call i_putc to print each character. */ while(!i_putc(channel, *(str + i))); } return(success); } /* formatted output string */ void i_printf(char *fmt, ...) { va_list argptr; char temp_buf[256]; va_start(argptr, fmt); vsprintf(temp_buf, fmt, argptr); sputs((uint8 *)temp_buf); va_end(argptr); }
diagnostic source code ks32c50100/5000a risc microcontroller 3 - 56 stringecho() demonstrate the usage of interrupted uart i/o functions. (listing 3-26). listing 3-26. (uart_test.c) void stringecho(uint32 channel) { uint8 *bp; /* uart test memory pointer */ uint32 sz,i; /* input string size */ uint8 ch; i = 0; do { i_printf("\r\r\rstring echo for interrupt test."); i_printf("\rinput characters will be echoed on console"); i_printf("\r\rinput %d : ",i); bp = (uint8 *)uarttxbuff; do { while((ch = i_getc(channel)) == null); *bp++ = ch; sz++; }while(ch != cr); bp = (uint8 *)uarttxbuff; i_printf("\recho %d: ",i); while((ch = *bp++) != cr) { while(!i_putc(channel,ch)); } i_printf("\rto escape, enter esc key : "); while((ch = i_getc(channel)) == null); i++; }while(ch != esc); }
ks32c50100/5000a risc microcontroller d iagnostic source code 3- 57 gdma (general direct memory access) gdma set-up figure 3-15 shows the gdma set-up for data transfer in interrupt mode. set-up gdma set interrupt vector for gdma transfer in interrupt mode. ex) syssetinterrupt(ngdma0_int, gdma0isr); set the gdmacon0/1 register values as following: run disable, mode selection, transfer width, source & destination address attributes, data transfer modes (memory to memory, uart to memory, memory to uart..) assign gdma source address value to the gdmasrc0/1 registers. in case of the uart transfer mode, uart receive buffer register address will be assigned to gdma source address. assign gdma destination address value to the gdmadst0/1 registers. in case of the memory to uart, the uart receive buffer register address will be assigned to gdma destination address. assign gdma transfer count value to the gmdadst0/1 registers. gdma transfer count value means the size of transferring byte data set gdma run enable bit in the gdmacon0/1 registers. ex) gdmacon0 |= 1; or set dma bit control address (= gdmacon base address +0x20 )to 1. using this bit control address, the other values in gdmacon register are not affected. gdma run figure 3-15. concept diagram for setting up gdma
diagnostic source code ks32c50100/5000a risc microcontroller 3 - 58 listing 3-27. (dma.c) /* dma memory to memory data transfer using interrupt */ void dcopy(uint32 dmadst, uint32 dmasrc,int size, int width) { uint32 dma_ con_set ; disable_int(ngdma0_int); /* disable gdma 0 interupt */ syssetinterrupt(ngdma0_int, gdma0isr); /* vector setup */ gdma0doneflag = 0; /* gdma transmit done flag */ gdmasrc0 = dmasrc; gdmadst0 = dmadst; gdmacnt0 = size; dma_con_set = gdma_mem2mem ; switch(width) { case 0 : dma_con_set |= gdma_width_btye; break; case 1 : dma_con_set |= gdma_width_hword; break; case 2 : default: dma_con_set |= gdma_width_w ord; break; } enable_int(ngdma0_int); /* enable gdma 0 interrupt */ gdmacon0 = dma_con_set | gdma_run; /* start run gdma0 */ // by interrupt mode while(!gdma0doneflag) ; } /* gdma0 transfer done interrput service routine */ void gdma0isr(void) { gdma0doneflag = 1; }
ks32c50100/5000a risc microcontroller d iagnostic source code 3- 59 32bit timers (timer0/1) the concept diagram for timer set-up (figure 3-16) shows how to configure the timer functions. these timers can be operated in interval or toggle mode. the timer output signals, tout0/tout1 can be monitored at p16[196] /p17[199]. the 32bit timer data register[tdatan] values are automatically reloaded to timer counter register [tcntn] whenever the timer interval expires. timer set-up diable timer interrput. ex) disable_int(ntimer1_int); set-up the timer interrupt service routine: interrupt mode will be configured to irq or fiq during the target boot-up time. ex) syssetinterrupt(ntimer1_int, tm1isr); set timer data registers (tdatan) with any wanted time duration. set timer mode register(tmodn): disable timer run, interval / toggle mode, initial tout value in toggle mode. enable timer interrupt ex) enable_int(ntimer1_int); set timer mode register(tmodn) for timer start: ex) timerstart(timer_dev1); enable timer signal output(tout0/1) if need it. general i/o pins, no 196/199, are assigned to tout0/1. tout0/1 signal frequency depend on the timer operation mode(interval or toggle) is calculated as follows: interval mode : ftout = fmclk/tdatan toggle mode : ftout = fmclk /(2*tdatan) timer run figure 3-16. concept diagram for timer set-up.
diagnostic source code ks32c50100/5000a risc microcontroller 3 - 60 listing 3-28. (timer.h) ? ? ? ? ? ? .. /*********************************************************/ /* usable macros functions & data structures */ /*********************************************************/ #define timer0stop() (tmod &= ~tm0_run) #define timer1stop() (tmod &= ~tm1_run) #define timer0start() (tmod |= tm0_run) #define timer1start() (tmod |= tm1_run) #define timerstart(t) ((t)? timer1start():timer0start()) #define timerstop(t) ((t)? timer1stop(): timer0stop()) #define tmdata(t) (t*0.001*fmclk-1) // t is time tick,unit[ms] #define t_data_ms(t) (t*0.001*fmclk-1) // t is time tick,unit[ms] #define t_data_us(t) (t*0.000001*fmclk-1) // t is time tick,unit[us] typedef struct { void (*timer_lisr)(); /* timer interrupt function pointer */ uint32 tm_channel; /* timer device */ uint32 tm_mode; /* timer mode register */ uint32 tm_data; /* timer data,timer range is 1~0xffffffff */ uint32 tm_out_port; /* enable timer output port */ }tm_param; typedef struct { volatile unsigned int tm_sec; volatile unsigned int tm_min; volatile unsigned int tm_hour; volatile unsigned int tm_mday; volatile unsigned int tm_mon; volatile unsigned int tm_year; }time; ? ? ? ? ? ? ? ? ? ? ? ? ?
ks32c50100/5000a risc microcontroller d iagnostic source code 3- 61 listing 3-29. (timer.c) /*************************************************************************/ /* */ /* name : tm_init(timer device, time periode) */ /* */ /* functions : initialize the timer0,1. */ /* */ /* examples : */ /* tm_init(timer_dev0,one_second/ticks_per_second); */ /* */ /* where, the timer_dev0 means timer0. */ /* one_second = 1000, */ /* ticks_per_second = 100, */ /* then timer0 timer periode become to 10ms. */ /* */ /* variables used */ /* */ /* */ /* history */ /* */ /* name date remarks */ /* */ /* in4maker 06-07-1999 created initial version 1.0 */ /* */ /*************************************************************************/ void tm_init(int timer_dev, int t) { if(timer_dev) /* for timer 1 */ { disable_int(ntimer1_int); syssetinterrupt(ntimer1_int, tm1isr); //iopdata &= ~(1<<17); /* output 0 to p17(tout1) */ //iopmod |= (1<<17); /* enable p17 to output port */ /* tout1 will be cleared */ tdata1 = t_data_ms(t); /* unit is [ms] */ tcnt1 = 0x0; tmod = tm1_toggle; /* toggle pulse will be out to port */ enable_int(ntimer1_int); /* timer interrupt enable */ //iopcon = (1<<30); /* timer1 output(tout1)enable */ } else /* for timer0 */ { disable_int(ntimer0_int); syssetinterrupt(ntimer0_int, tm0isr); //iopdata &= ~(1<<16); /* output 0 to p16(tout0) */ //iopmod |= (1<<16); /* enable p16 to output port */ /* tout0 will be cleared */ tdata0 = t_data_ms(t);
diagnostic source code ks32c50100/5000a risc microcontroller 3 - 62 tcnt0 = 0x0; tmod = tm0_toggle; enable_int(ntimer0_int); //iopcon = (1<<29); /* timer0 output(tout0)enable */ } } /*************************************************************************/ /* */ /* name : tm0isr() */ /* */ /* functions : timer0 interrupt service routine. */ /* */ /*************************************************************************/ void tm0isr(void) { clk_tick0++; if(clk_tick0 == ticks_per_second) { clk_tick0 = 0; if(tm0.tm_sec++ > 59) { tm0.tm_sec = 0; if(tm0.tm_min++ > 59) { tm0.tm_min = 0; if(tm0.tm_hour++ > 23) { tm0.tm_hour = 0; if(tm0.tm_mday++ > 30) { tm0.tm_mday = 0; if(tm0.tm_mon++ > 11) { tm0.tm_mon = 0; tm0.tm_year++; } } } } } /* 4 means digit number for led display */ iopdata = ~(1< ks32c50100/5000a risc microcontroller d iagnostic source code 3- 63 i/o ports the general i/o ports(p0~p17) shared with a special function such as an external interrupt request, an external dma request & acknowledge and timer signal outputs. i/o port mode can be configured by i/o port mode register(iopmod). but, the shared function will be configured by the iopcon register not by iopmod. configure the i/o port set i/o port mode register, iopmod: p0~ p17 can be configured input or outputs . disable interrupt setup interrupt service functions for external interrupt , external dma interrupt and timer interrupt etc,,,. if needed. set i/o port control register,iopcon: the p8~p17 have the shared with a special function such as a external interrupt input, an external dma request & acknowledge, timer signal output. these shared function mode is determined by the iopcon not iopmod. enable interrupt read and write i/o data register,iopdata: interrupt will be served if it is configured. figure 3-17. concept diagram for the configuring of i/o port
diagnostic source code ks32c50100/5000a risc microcontroller 3 - 64 high-level data link controller for KS32C5000(a) hdlc diagnostic code function for KS32C5000(a) the diagnostic source code for the hdlc (high-level data link controller) is composed of four files, hdlc.h, hdlc.c, hdlcinit.c, and hdlclib.c. hdlc.h : definition file for hdlc diagnostic code. hdlc.c : the main functions for hdlc diagnostic test. hdlcinit.c : initialize hdlc and hdma controller for normal operating environment, each interrupt service routine. hdlclib.c : the library functions for hdlc diagnostic code. definitions of hdlc for KS32C5000(a) define macro function for each hdlc controller control and status register address, and some simple function for control hdlc controller. the definition source code is described in listing 3-30 . listing 3-30. definition for hdlc for KS32C5000(a) (hdlc.h) // macro function for define hdlc registers #define hcon0(channel) (vpint(base_addr+0x7000 + channel*0x1000)) #define hcon1(channel) (vpint(base_addr+0x7004 + channel*0x1000)) #define hstat(channel) (vpint(base_addr+0x7008 + channel*0x1000)) #define hinten(channel) (v pint(base_addr+0x700c + channel*0x1000)) #define htxfifoc(channel) (vpint(base_addr+0x7010 + channel*0x1000)) #define htxfifot(channel) (vpint(base_addr+0x7014 + channel*0x1000)) #define hrxfifo(channel) (vpint(base_addr+0x7018 + channel*0x1000)) #define hsadr(channel) (vpint(base_addr+0x701c + channel*0x1000)) #define hbrgtc(channel) (vpint(base_addr+0x7020 + channel*0x1000)) #define hprmb(channel) (vpint(base_addr+0x7024 + channel*0x1000)) #define hdmatxma(channel) (vpint(base_addr+0x7028 + channel*0x1000)) #define hdmarxma(channel) (vpint(base_addr+0x702c + channel*0x1000)) #define hdmatxcnt(channel) (vpint(base_addr+0x7030 + channel*0x1000)) #define hdmarxcnt(channel) (vpint(base_addr+0x7034 + channel*0x1000)) #define hdmarxbcnt(channel) (vpint(base_addr+0x7038 + channel*0x1000)) // macro function for hdlc controller control #define hdlc_tx_enable(channel) hcon0(channel) |= txen #define hdlc_rx_enable(channel) hcon0(channel) |= rxen #define hdma_tx_enable(channel) hcon0(channel) |= dtxen #define hdma_rx_enable(channel) hcon0(channel) |= drxen #define hdlc_loopback_enable(channel) hcon1(channel) |= txloop #define hdlc_loopback_disable(channel) hcon1(channel) &= ~txloop
ks32c50100/5000a risc microcontroller d iagnostic source code 3- 65 hdlc initialize for KS32C5000(a) the hdlc and hdma should be initialized before getting into operation. hdlcinitialize(), and hdlcportinit() function is used for this initialization. in the following, describe the contents of this function. in the high-speed operation of hdlc, hdma can be used for transferring and receiving data to memory and transfer the transmit data to hdlc. the hdlc can support full duplex operation, and speed up to 4mbps using an external/internal clock. when you use hdlc controller to your system, you need to set the hdlc, and hdma controller to work properly. when we setup hdlc controller, we use device_entry structure, the device_entry structure has all parameter that should be setup for normal operation. the device_entry structure is described in listing 3-31 . listing 3-31. device_entry structure for KS32C5000(a) (hdlc.h) typedef struct hdlc_device { u32 hdlc_port ; // hdlc port number u32 hdlc_baud ; // hdlc baudrate u32 hdlc_data_format ; // hdlc data format, nrz,nrzi,fm0,fm1,menchester u32 hdlc_tx_mode ; // hdlc tx dma or interrupt mode u32 hdlc_rx_mode ; // hdlc rx dma or interrupt mode u32 hdlc_tx_output_clk ; // tx clock pin output source, rx_clock,brgout1,2,3 // dplloutt, dplloutr u32 hdlc_tx_clk ; // tx clock source,txc pin, rxc pin, dplloutt, brgout1,2,3 u32 hdlc_rx_clk ; // rx clock source,txc pin, rxc pin, dplloutt, brgout1,2,3 u32 hdlc_tx_clk_pos ; // tx clock polarity, only for KS32C5000a u32 hdlc_rx_clk_pos ; // rx clock polarity, only for KS32C5000a u32 hdlc_station_addr ; } hdlc_device_entry ; the initialize parameter for each hdlc controller is described in source code listing 3-32 . after initialize the hdlc parameter, the hdlcportinit() function is used for initialize each port with initialization parameter value. and, we also need to setup the interrupt vector table for each hdlc controller interrupt source.
diagnostic source code ks32c50100/5000a risc microcontroller 3 - 66 listing 3-32. hdlcinitialize( ) function (hdlcinit.c) /* * function : hdlcinitialize * description : hdlc controller initialize */ void hdlcinitialize(void) { hdlc_device_entry *dev_entry[hdlcportnum] ; int channel; disable_int(nhdlca_int); disable_int(nhdlcb_int); // step 1. set hdlc channel a initialize parameter dev_entry[hdlca] = (hd lc_device_entry *)&hdlc_dev[hdlca] ; dev_entry[hdlca]->hdlc_port = hdlca ; dev_entry[hdlca]->hdlc_baud = 64000 ; dev_entry[hdlca]->hdlc_data_format = df_nrz ; dev_entry[hdlca]->hdlc_tx_mode = mode_dma ; dev_entry[hdlca]->hdlc_rx_mode = mode_dma ; dev_entry[hdlca]->hdlc_tx_output_clk = txoclk_brg1 ; dev_entry[hdlca]->hdlc_tx_clk = txclk_brg1 ; dev_entry[hdlca]->hdlc_rx_clk = rxclk_rxc ; dev_entry[hdlca]->hdlc_station_addr = hdlc_station_addr ; // tx clock polarity, only for KS32C5000a, // when set 0 the polarity is same as KS32C5000 dev_entry[hdlca]->hdlc_tx_clk_pos = txcneg ; // rx clock polarity, only for KS32C5000a, // when set 1 the polarity is same as KS32C5000 dev_entry[hdlca]->hdlc_rx_clk_pos = rxcpos ; // step 2. set hdlc channel b initialize parameter dev_entry[hdlcb] = (hdlc_device_entry *)&hdlc_dev[hdlcb] ; dev_entry[hdlcb]->hdlc_port = hdlcb ; dev_entry[hdlcb]->hdlc_baud = 64000 ; dev_entry[hdlcb]->hdlc_data_format = df_nrz ; dev_entry[hdlcb]->hdlc_tx_mode = mode_dma ; dev_entry[hdlcb]->hdlc_rx_mode = mode_dma ; dev_entry[hdlcb]->hdlc_tx_output_clk = txoclk_brg1 ; dev_entry[hdlcb]->hdlc_tx_clk = txclk_brg1 ; dev_entry[hdlcb]->hdlc_rx_clk = rxclk_rxc ; dev_entry[hdlcb]->hdlc_station_addr = hdlc_station_addr ; // tx clock polarity, only for KS32C5000a, // when set 0 the polarity is same as KS32C5000 dev_entry[hdlcb]->hdlc_tx_clk_pos = txcneg ; // rx clock polarity, only for KS32C5000a,
ks32c50100/5000a risc microcontroller d iagnostic source code 3- 67 // when set 1 the polarity is same as KS32C5000 dev_ent ry[hdlcb]->hdlc_rx_clk_pos = rxcpos ; // step 3. initialize each hdlc port for(channel=hdlca ; channel<=hdlcb ; channel++) { if ( !hdlcportinit(dev_entry[channel]) ) print("\n hdlc channel [%d] initialize error",channel) ; } // step 4. setup interrupt for hdlc syssetinterrupt(nhdlca_int, hdlca_isr ); syssetinterrupt(nhdlcb_int, hdlcb_isr ); // step 5. enable hdlc interrupt enable_int(nhdlca_int); enable_int(nhdlcb_int); } after setup hdlc parameter, the main hdlc initialization is performed by hdlcportinit() function. the detail of hdlc initialization function is described in source code listing 3-33 , and figure 3-19 . listing 3-33. hdlcportinit() function for KS32C5000(a) (hdlcinit.c) /* * function : hdlcportinit * description : hdlc port initialize */ int hdlcportinit(hdlc_device_entry *device) { u32 txinterruptenableflag ; u32 rxinterruptenableflag ; u32 channel ; channel = device->hdlc_port ; // step 1. reset hdlc controller and hdlc dma hcon0(channel) = txrs | rxrs | dtxrs | drxrs ; // step 2. set station address // this register only used when enable rxasen. now, we didn't use hsadr(channel) = device->hdlc_station_addr ; // step 3. set baud rate generater constant value hbrgtc(channel)= fmclk/(2*device->hdlc_baud)-1; // step 4. set preamble value for nrz code hprmb(channel) = hdlc_preamble ; // step 5. set hdlc control register 1 hcon1(channel) = ghcon1 | \
diagnostic source code ks32c50100/5000a risc microcontroller 3 - 68 device->hdlc_data_format |\ device->hdlc_tx_output_clk |\ device->hdlc_tx_clk |\ devi ce->hdlc_rx_clk ; // step 6. set hdlc control register 0 // baud-rate generator enable, dpll enable, tx/rx enable hcon0(channel) = ghcon0 | \ device->hdlc_tx_clk_pos | \ device->hdlc_rx_clk_pos ; // step 7. tx, and rx buffer descriptor initialize txbdinitialize(channel) ; rxbdinitialize(channel) ; // step 8. enable hdlc transmit controller hdlc_tx_enable(channel); // step 9. setup hdlc and hdma for receive operation hdlc_rx_init(channel) ; // step 10. set hdlc interrupt enable register if ( device->hdlc_tx_mode == mode_dma ) txinterruptenableflag = dtxie | txuie | dtxabie | \ dtxstopie | txuie ; else txinterruptenableflag = txuie ; if ( device->hdlc_rx_mode == mode_dma ) rxinterruptenableflag = drxie | rxabie | rxferrie | rxovie | \ drxstopie | drxabie ; else rxinterruptenableflag = rxabie | rxferrie | rxovie | rxfaie | rxfvie ; ghinten |= txinterruptenableflag | rxinterruptenableflag ; hinten(channel) = ghinten ; // step 11. clear hdlc status hstat(channel ) |= hstat(channel) ; return 1 ; }
ks32c50100/5000a risc microcontroller d iagnostic source code 3- 69 hdlc initialize start reset hdlc and hdma controller set station address set baud rate set preamble value set hdlc control register 1 set hdlc control register 0 set hdlc interrupt enable register clear hdlc status hdlc initialize finished hdlc control register 1 1. burst size 2. little/big operation 3. memory increment or decrement 4. brg source clock 5. dpll source clock 6. hdlc data format 7. hdlc tx clock source 8. hdlc rx clock source 9. hdlc tx clock output pin source hdlc control register 0 1. brg clock generation enable 2. dpll enable(option) 3. set rts, and dtr 4. tx clock polarity 5. rx clock polarity get buffer pointer to receive check usable buffer check dma mode or interrupt mode enable hdlc rx dma set data buffer for interrupt mode setup hdlc and hdma for rx enable hdlc tx controller initialize tx and rx buffer descriptor figure 3-19. hdlc initialization flow
diagnostic source code ks32c50100/5000a risc microcontroller 3 - 70 the each step of hdlc initializing function is described as followings. step 1. reset hdlc controller and hdlc dma first of all, it is necessary to reset hdlc and dma controller, which initialize registers as default values. step 2. set station address the station address can be used when rxasen bit is setting to address search. step 3. set baud rate generater constant value to brgtc step 4. set preamble value step 5. set hdlc control register 1 ( table 3-5) table 3-5. hdlc control register 1 initialize control bit name description in sample code control behavior df selecting data format nrz,nrzi,fm0,fm1, and manchester nrz nrz data format will be used for data encoding/decoding for each channel. txlittle selecting endian mode select whether data bytes are swapped or not between system bus and hdlc tx/rx fifo txbig the transmitted data will be a big endian format. rxlittle rxbig we assume the data which will be received as big endian format. rxclk selecting rx clock rx clock can be selected from brg, dplloutr, or external txc/rxc pin. rxclk_rxc external clock to rxc pin is selected as rx clock. txclk selecting tx clock tx clock can be selected from brg, dplloutt, or external txc/rxc pin. txclk_brg1 brgout2 clock generated by brg block is selected as tx clock. txcops selecting txc pin as output txoclk_brg1 brg1 clock is output tot txc pin. brgclk internal brg clock for tx/rx clock brg source clock can be select between mclk and rxc pin. when use brg clock, you should enable brgen bit on hcon0 register brgclk_mclk system main clock selected as brg source clock.
ks32c50100/5000a risc microcontroller d iagnostic source code 3- 71 in the hdlc, brg output, or dpll output clock can be used (brg or dpll should be enabled). brg output clock is depend on the time constant value which should be written to hbrgtc register. when use brg clock, brgout1 is faster than 32 times than brgout3, and 16 times than brgout2 in same time constant value. when set the hdlc clock, another consideration is data type. if incoming data type is nrz or nrzi, the source clock of the dpll must be 32 times faster than rxd. in fm or menchester, 16 times faster clock is needed. using the dpll output clock, dplloutt for tx clock and dplloutr fro rx clock can be selected respectively. the hdlc clock diagram is depicted in figure 3-20 . brg dpll mclk rxc pin mclk rxd brgtc value brgout1 brgout2 rxc pin txc pin dplloutt dplloutr figure 3-20. hdlc internal clock block diagram step 6. set hdlc control register 0 in the hdlc control register 0, brg(baud rate generator) counter should be enabled when use brg clock. and, in the KS32C5000a has some different txc, and rxc pin input polarity from KS32C5000. so, when you use KS32C5000a, you should set the clock polarity value. [note] hardware flow control hdlc control register 0(hcon0) register has two bits to manage hardware flow control. txdtr bit directly affects the ndtr pin output state if txen bit is enabled. when txdtr bit is cleared, ndtr goes high. and autoen bit controls the function of ndcd and ncts. step 7. tx, and rx buffer descriptor initialize. this buffer descriptor is used for receive and transmit data buffer, all receive and transmit operation use this buffer descriptor. the buffer descriptor structure is described in listing 3-34 , and figure 3-21 .
diagnostic source code ks32c50100/5000a risc microcontroller 3 - 72 frame data pointer #1 length field status field next frame descriptor frame data pointer #1 length field status field next frame descriptor frame data pointer #1 length field status field next frame descriptor figure 3-21. hdlc buffer descriptor structure for KS32C5000(a) listing 3-34. hdlc buffer descriptor structure for KS32C5000(a) (hdlcinit.c) // tx/rx buffer descriptor structure typedef struct bd { u32 bufferdataptr; u32 s tatusfield ; u32 lengthfield ; u32 nextbufferdescriptor ; } sbufferdescriptor; the hdlc tx/rx buffer descriptor, and data buffer area should be non-cacheable, because hdlc dma can update the value, so when we initialize buffer descriptor, use noncache(= 0x4000000) for non-cacheable access. the listing 3-35 , and listing 3-36 show the detail operation of setup hdlc tx/rx buffer descriptor. the default owner of transmit hdlc buffer descriptor is cpu, and the default owner of receive hdlc buffer descriptor owner is dma, after receive frame, in the interrupt service routine for receive operation, buffer descriptor owner is changed to cpu owner, then it can be processed by cpu(user receive operation), after process this received frame, cpu change buffer owner to dma again to receive next frame. when transmit a frame, cpu change the owner to dma after initialize frame data to buffer, after transmit a frame, in the interrupt service routine for transmit operation, the owner is changed to cpu again to use next frame transmit buffer.
ks32c50100/5000a risc microcontroller d iagnostic source code 3- 73 listing 3-35. txbdinitialize() function for KS32C5000(a) (hdlcinit.c) /* * function : void txbdinitialize(u32 channel) ; * description : initialize tx buffer descriptor area-buffers. */ void txbdinitialize(u32 channel) { sbufferdescriptor *pbufferdescriptor; sbufferdescriptor *pstartbufferdescriptor; sbufferdescriptor *plastbufferdescriptor = null; u32 bufferdataaddr; u32 i; // get buffer descriptor's base address. // +0x4000000 is for setting this area to non-cacheabl e area. gctxbdptr[channel] = (u32)txbdabase[channel] + noncache ; pctxbdptr[channel] = (u32)txbdabase[channel] + noncache ; // get transmit buffer base address. hdmatxma(channel) = bufferdataaddr = (u32)txbabase[channel] + noncache ; // generate linked list. pbufferdescriptor = (sbufferdescriptor *) gctxbdptr[channel]; pstartbufferdescriptor = pbufferdescriptor; for(i=0; i < maxtxbufferdescriptor; i++) { if(plastbufferdescriptor == null) plastbufferdescriptor = pbufferdescriptor; else plastbufferdescriptor->nextbufferdescriptor = (u32)pbufferdescriptor; pbufferdescriptor->bufferdataptr = (u32)(bufferdataaddr & bownership_cpu); pbufferdescriptor->statusfield = (u32)0x0; pbufferdescriptor->lengthfield = (u32)0x0; pbufferdescriptor->nextbufferdescriptor = null; plastbufferdescriptor = pbufferdescriptor; pbufferdescriptor++; bufferdataaddr += sizeof(shdlcframe); } // end for loop // make buffer descriptor to ring buffer type. pbufferdescriptor--; pbufferdescrip tor->nextbufferdescriptor = (u32)pstartbufferdescriptor; }
diagnostic source code ks32c50100/5000a risc microcontroller 3 - 74 listing 3-36. rxbdinitialize() function for KS32C5000(a) (hdlcinit.c) /* * function : void rxbdinitialize(u32 channel) ; * description : initialize rx buffer descriptor area-buffers. */ void rxbdinitialize(u32 channel) { sbufferdescriptor *pbufferdescriptor; sbufferdescriptor *pstartbufferdescriptor; sbufferdescriptor *plastbufferdescriptor = null; u32 bufferdataaddr; u32 i; // get buffer descriptor's base address. // +0x4000000 is for setting this area to non-cacheable area. gcrxbdptr[channel] = (u32)rxbdabase[channel] + noncache ; pcrxbdptr[channel] = (u32)rxbdabase[channel] + noncache ; // get transmit buffer base address. hdmarxma(channel) = bufferdataaddr = (u32)rxbabase[channel] + noncache ; // generate linked list. pbufferdescriptor = (sbufferdescriptor *) gcrxbdptr[channel]; pstartbufferdescriptor = pbufferdescriptor; for(i=0; i < maxrxbufferdescriptor; i++) { if(plastbufferdescriptor == null) plastbuff erdescriptor = pbufferdescriptor; else plastbufferdescriptor->nextbufferdescriptor = (u32)pbufferdescriptor; pbufferdescriptor->bufferdataptr = (u32)(bufferdataaddr | bownership_dma | noncache ); pbufferdescriptor->statusfield = (u32)0x0; pbufferdescriptor->lengthfield = (u32)0x0; pbufferdescriptor->nextbufferdescriptor = null; plastbufferdescriptor = pbufferdescriptor; pbufferdescriptor++; bufferdataaddr += sizeof(shdlcframe); } // end for loop // make buffer descriptor t o ring buffer type. pbufferdescriptor--; pbufferdescriptor->nextbufferdescriptor = (u32)pstartbufferdescriptor; }
ks32c50100/5000a risc microcontroller d iagnostic source code 3- 75 step 8. enable hdlc transmit controller step 9. setup hdlc and hdma for receive operation this step setup the hdlc and hdma can receive frame to reserved buffer. the step of setup flow of hdlc and hdma can receive is described in below. 1. get hdlc device entry pointer at the first time get the hdlc device entry point to control hdlc buffer. 2. get receive buffer pointer from global variable get the pointer of receive buffer descriptor, and data buffer from global variable that has current buffer descriptor pointer 3. check rx dma ownership check ownership of buffer descriptor that from current buffer descriptor pointer, if ownership is cpu, then current buffer can used for received buffer, but if this buffer pointer is owned by dma, then just exit this initialize routine with error information. 4. clear ownership bit for dma if current buffer can we use, then we can get data buffer pointer, but when set the owner bit, this is not a visible address area, the clear operation is only need to get data pointer address. 5. setup rx dma and data buffer if receive mode is dma mode, then setup receive hdma to can receive a frame from hdlc controller and enable the hdlc receive operation, but if receive mode is interrupt method, then we only get the data pointer that can be used for temporary received data buffer. 6. receive enable after setup hdlc and hdma controller, we can enable hdlc controller can receive the incomming data. the source code for hdlc and hdma initialize function for receive operation is described in listing 3-37 .
diagnostic source code ks32c50100/5000a risc microcontroller 3 - 76 listing 3-37. hdlc_rx_init() function for KS32C5000(a) (hdlcinit.c) /* * function : hdlc_rx_init * description : hdlc rx initialize * return 1 : hdlc receive initialize ok * return 0 : hdlc receive initialize fail */ int hdlc_rx_init(u32 channel) { sbufferdescriptor *crxbdptr ; hdlc_device_entry *dev ; u32 databuffer; // step 1. get hdlc devic e entry pointer dev = (hdlc_device_entry *)&hdlc_dev[channel] ; // step 2. get receive buffer pointer from global variable crxbdptr = (sbufferdescriptor *)gcrxbdptr[channel] ; databuffer = (u32)crxbdptr->bufferdataptr ; // step 3. check rx dma ownership if ( ((u32)(crxbdptr->bufferdataptr) & bownership_dma) ) { // step 4. clear ownership bit for dma databuffer = (u32)(crxbdptr->bufferdataptr & bownership_cpu ) ; // step 5. setup rx dma and data buffer if ( dev->hdlc_rx_mode == mode_dma ) { hdmarxbcnt(channel) = 0x0 ; hdmarxma(channel) = databuffer ; hdmarxcnt(channel) = sizeof(shdlcframe) ; hdma_rx_enable(channel) ; } else { modeint_rxdatabuffer[channel] = (u32 *)databuffer ; modeint_rxdatasize[channel] = 0 ; } // step 6. receive enable hdlc_rx_enable(channel) ; return 1 ; } else return 0 ; // buffer full state, so can't use this buffer before get used }
ks32c50100/5000a risc microcontroller d iagnostic source code 3- 77 step 10. set hdlc interrupt enable register hdlc has many interrupt source, hdlc tx, hdlc rx, hdma tx, and hdma rx interrupt source, this routine enable each interrupt source for each tx/rx method. step 11. clear hdlc status register bit value. note: the way to use status register there are three kinds of bits in status register. one sort of these bits are cleared automatically when this bit indicating status is cleared. these status bits are txfa, txcts, rxfa, and rxdcd. the second kinds of bits are cleared by reading fifo or this bit, the rxfap, fxaerr,rxfv, and rxferr bits are cleared by reading rxfifo in interrupt mode, and cleared by read this bit in dma mode. and, the other all status is cleared by cpu writing 1. transmit hdlc frame with KS32C5000(a) after setting all control register and hdma transmit buffer descriptor, you can transmit packet. at the first time you should prepare frame to transmit. the sample code for prepare frame is shown in listing 3-38 . listing 3-38. transmit_frame() function for KS32C5000(a) (hdlclib.c) ? ? ? ? // step 1. set destination address fields framebuffer.header .address[0] = 0x12 ; framebuffer.header.address[1] = 0x34 ; framebuffer.header.address[2] = 0x45 ; framebuffer.header.address[3] = 0x67 ; // step 2. set control field framebuffer.header.control[0] = 0xff ; // step 3. set hdlc frame data for (i=0 ; i< (size-(sizeof(shdlcheader))) ; i++) framebuffer.information[i] = (u8)(i & 0xff) ; // sample code, just has sequence ? . // step 4. send hdlc frame if (!sendhdlcframe(channel,(u8 *)&framebuffer,size) ) print("\n hdlc %d send error",channel) ; ? ? ? ? ? the sendhdlcframe() function is used for transmit hdlc frame. the source code of sendhdlcframe() function is listed in listing 3-39 , and the transmit flow of hdlc frame is depicted in figure 3-22 . in the dma mode, hdlc transmit is performed by hdma without cpu intercept, but in the interrupt mode hdlc transmit operation, cpu write the frame data to hdlc transmit fifo. hdlc controller has to register to write frame data to hdlc fifo. the htxfifoc, and htxfifot is used for this purpose. when transmit a data, cpu can write the frame data to the htxfifoc, txfifo frame continue register, and at the end of transmit cpu write last frame data to htxfifot, txfifo frame terminate register . the source code for write transmit frame data to fifo, writedatatofifo() is listed in listing 3-40 . this function is always called from hdlc interrupt service routine for fifo available interrupt. the hdlc tx fifo write flow is depicted in figure 3-23 .
diagnostic source code ks32c50100/5000a risc microcontroller 3 - 78 listing 3-39. sendhdlcframe() function for KS32C5000(a) (hdlcinit.c) /* * function : sendhdlcframe * description : send hdlc frame */ int sendhdlcframe(u32 channel, u8 *data, int size) { sbufferdescriptor *ctxbdptr ; hdlc_device_entry *dev ; u32 *databufferptr ; u8 *databuffer ; // step 1. get device entry pointer dev = (hdlc_device_entry *)&hdlc_dev[channel] ; // step 2. get transmit buffer descriptor pointer ctxbdptr = (sbufferdescriptor *)pctxbdptr[channel] ; // step 3. get data buffer pointer databufferptr = (u32 *)ctxbdptr->bufferdataptr ; dat abuffer = (u8 *)ctxbdptr->bufferdataptr ; // step 4. check dma ownership, if setted to 1 then exit send frame if ( ((u32)ctxbdptr->bufferdataptr & bownership_dma) ) return 0 ; // step 5. copy tx frame data to frame buffer ctxbdptr->lengthfield = size ; memcpy ((u8 *)databuffer,(u8 *)data,size); // step 6. change ownership to dma ctxbdptr->bufferdataptr |= bownership_dma; // step 7. change current buffer descriptor pointer pctxbdptr[channel] = (u32)ctxbdptr->nextbufferdescriptor ; // step 8. set hdlc transmit dma or transmit buffer if ( dev->hdlc_tx_mode == mode_dma ) { // setup hdlc transmit dma hdma_tx_init(channel,(u32)databufferptr,size) ; hdma_tx_enable(channel); } else { // setup transmit buffer and size to transmit modeint_txdatabuffer[channel] = (u8 *)databuffer ; modeint_txdatasize[channel] = size ; // enable transmit fifo avaliable interrupt hinten(channel) |= txfaie ; } return 1 ; }
ks32c50100/5000a risc microcontroller d iagnostic source code 3- 79 listing 3-40. writedatatofifo() function for KS32C5000(a) (hdlcinit.c) /* * function : writedatatofifo * description : write frame data to hdlc tx fifo * this function is used only interrupt mode transmit */ int writedatatofifo(u32 channel) { int i, j ; u32 *data ; u8 *data ; for (i=0 ; i<4 ; i++) { if ( modeint_txdatasize[channel] > 4 ) { // read data buffer pointer to transmit data = (u32 *)modeint_txdatabuffer[channel] ; // write tx frame data to fifo htxfifoc(channel) = *data ; // increase data pointer modeint_txdatabuffer[chann el] += 4 ; // decrement word modeint_txdatasize[channel] -= 4 ; } else { // excuted when left transmit byte is 4 or under 4 byte // disable transmit fifo avaliable interrupt hinten(channel) &= ~txfaie ; if (modeint_txdatasize[channel] == 4 ) { // if lefted transmit data is 1 word, then write // word data to htxfifot register data = (u32 *)modeint_txdatabuffer[channel] ; htxfifot(channel) = *data ; modeint_txdatasize[channel] -= 4 ; // decrement word } el se { // get byte data pointer data = (u8 *)modeint_txdatabuffer[channel] ; hdlctxfifot = (u8 *)&htxfifot(channel) ; hdlctxfifoc = (u8 *)&htxfifoc(channel) ; // process under 4 byte data for ( j=0 ; j<4; j++) { modeint_txdatasize[channel] -- ;// decrement byte if (modeint_txdatasize[channel] > 0) { *hdlctxfifoc = *data++ ; } else { // end of frame data
diagnostic source code ks32c50100/5000a risc microcontroller 3 - 80 *hdlctxfifot = *data++ ; break ; } } } return 0 ; // return end of fra me transfer } } return 1 ; // return not end of frame transfer }
ks32c50100/5000a risc microcontroller d iagnostic source code 3- 81 exit with send error call sendhdlcframe() function to transmit hdlc frame get hdlc device entry point copy frame data to frame buffer cpu owner ? change ownership to dma hdlc interrupt with hdma tx stop yes get buffer descriptor pointer get data buffer pointer change current buffer descriptor to next pointer dma mode or interrupt mode ? tx hdma initialize enable hdlc tx controller set transmit buffer enable hdlc tx fifo avaliable interrupt no transmit frame get current buffer descriptor clear length and status field change ownership to cpu get next buffer descriptor exit hdlc interrupt service routine for tx hdlc interrupt with txfifo avaliable dma mode interrupt mode write frame data to fifo transfer finished ? finished not finished figure 3-22. hdlc transmit frame data flow for KS32C5000(a)
diagnostic source code ks32c50100/5000a risc microcontroller 3 - 82 write frame data to fifo (4 word) start bigger than 1 word ? write 1 word data to htxfifoc register disable txfifo available interrupt increment 1 word data pointer calcurate remaind byte to tx 4 word tx finished ? write last 1 word to htxfifot register check remaind byte write last 1 byte to htxfifot register write 1 byte to htxfifoc register finished finished all tx data transfer finished no under 1 word 1 word no yes no yes last byte ? figure 3-23. hdlc tx fifo write flow for KS32C5000(a)
ks32c50100/5000a risc microcontroller d iagnostic source code 3- 83 finally, when you transmit hdlc frame, you can follow this step. step 1. get device entry pointer step 2. get transmit buffer descriptor pointer step 3. get data buffer pointer step 4. check dma ownership, if setted to 1 then exit send frame step 5. copy tx frame data to frame buffer step 6. change ownership to dma step 7. change current buffer descriptor pointer to next pointer step 8. set hdlc transmit dma or transmit buffer in the dma mode, all data transfer of hdlc frame is performed by hdma, but in the interrupt mode, all data transfer is performed by cpu, when txfifo available interrupt is occurred. the interrupt service routine source code for hdlc transmit operation is listed in listing 3-41 . listing 3-41. interrupt service routine for hdlc tx operation with KS32C5000(a) (hdlcinit.c) ? ? ? ? . // 6. hdlc transmit dma mode complete if ( inthdlcstatus & (dtxstop | dtxabt) ) { if ( inthdlcstatus & dtxstop ) { ghdlctxstatus[channel].dmatxstop++ ; hstat(channel) |= dtxstop ; } if ( inthdlcstatus & dtxabt ) { ghdlctxstatus[channel].dmatxabt++ ; hstat(channel) |= dtxabt ; } do { // step 1. get current transmit buffer descriptor pointer // and length ctxbdptr = (sbufferdescriptor *)gctxbdptr[channel]; txlength = ctxbdptr->lengthfield ; // step 2. clear length and status field ctxbdptr->lengthfield = (u32)0x0; ctxbdptr->statusfield = (u32)0x0; // step 3. get next buffer descriptor gctxbdptr[channel] = (u32)ctxbdptr->nextbufferdescriptor ; // step 4. clear dma owner to cpu ctxbdptr->bufferdataptr &= bownership_cpu ; } while (pctxbdptr[channel] == gctxbdptr[channel]) ; } // 7. hdlc transmit interrupt mode
diagnostic source code ks32c50100/5000a risc microcontroller 3 - 84 if (dev->hdlc_tx_mode == mode_interrupt) { if (inthdlcstatus & txfa) { ghdlctxstatus[channel].txfifoavailable++ ; if ( modeint_txdatasize[channel] > 0) // step 1. write 4 word frame data to fifo if ( !writedatatofifo(channel) ) { // step 2. get current receive buffer descriptor point ctxbdptr = (sbufferdescriptor *)gctxbdptr[channel]; txlength = ctxbdptr->lengthfield ; // step 3. clear length and status field ctxbdptr->lengthfield = (u32)0x0; ctxbdptr->statusfield = (u32)0x0; // step 4. get next buffer descriptor gc txbdptr[channel] = (u32)ctxbdptr->nextbufferdescriptor ; // step 5. clear owner to cpu ctxbdptr->bufferdataptr &= bownership_cpu ; } } } // 8. hdlc transmit status if ( inthdlcstatus & ( txfc | txu | txcts | txscts ) ) { if ( inthdlcstatus & txfc ) { ghdlctxstatus[channel].txframecomplete++ ; hstat(channel) |= txfc ; } if ( inthdlcstatus & txu ) { ghdlctxstatus[channel].txunderrun++ ; hstat(channel) |= txu ; } if (inthdlcstatus & txcts) ghdlctxstatus[ch annel].txlevelofcts++ ; if (inthdlcstatus & txscts) { ghdlctxstatus[channel].txtransitionofcts++ ; } } ? ? ? ? ? .
ks32c50100/5000a risc microcontroller d iagnostic source code 3- 85 receive hdlc frame with KS32C5000(a) after setting all control register and hdlc receive buffer descriptor, you can receive hdlc frame, at the first time, receive hdlc buffer descriptor has dma owner, after receive, in the interrupt service routine, cpu change this owner bit to cpu, then cpu can use this buffer descriptor and data buffer to process. after process the data on this buffer descriptor, cpu should change the owner to dma. as same as hdlc frame data transfer operation, hdlc receive operation can be used with dma, and interrupt mode. in the dma mode, hdlc controller can receive incoming frame without cpu intervention, but in the interrupt mode operation, cpu should read the received data from hdlc rxfifo. the source code for interrupt service routine is listed in listing 3-42 . listing 3-42. interrupt service routine for hdlc rx operation with KS32C5000(a) (hdlcinit.c) ? ? ? ? . // 3. process hdma receive operation // this routine is used when hdlc dma mode receive operation if ( inthdlcstatus & ( drxstop | drxabt) ) { if ( inthdlcstatus & drxstop ) { ghdlcrxstatus[channel].dmarxstop++ ; hstat(channel) |= drxstop ; } else if ( inthdlcstatus & drxabt ) { ghdlcrxstatus[channel].dmarxabt++ ; hstat(channel) |= drxabt ; } // step 1. get current receive buffer descriptor point crxbdptr = (sbufferdescriptor *)gcrxbdptr[channel]; // step 2. clear owner to cpu crxbdptr->bufferdataptr &= bownership_cpu ; // step 3. get length and status crxbdptr->lengthfield = rxlength = hdmarxbcnt(channel) ; crxbdptr->statusfield = inthdlcstatus ; // step 4. get next buffer descriptor gcrxbdptr[channel] = (u32)crxbdptr->nextbufferdescriptor ; // step 5. initialize hdlc dma for receive hdlc_rx_init(channel) ; } // 4. process hdlc receive operation // this routine is used when hdlc interrupt mode receive operation if (dev->hdlc_rx_mode == mode_inte rrupt) { if (inthdlcstatus & (rxfa | rxfv | rxferr) ) { if (inthdlcstatus & rxfa)
diagnostic source code ks32c50100/5000a risc microcontroller 3 - 86 ghdlcrxstatus[channel].rxfifoavalable++ ; if (inthdlcstatus & (rxfv | rxferr) ) { if (inthdlcstatus & rxfv) ghdlcrxstatus[channel].rxlastframevalid++ ; if ( inthdlcstatus & rxferr ) ghdlcrxstatus[channel].rxframeerror++ ; // step 1. read received data from hdlc receive fifo entry readdatafromfifo(channel,(hstat(channel)&0xf)) ; // step 2. get current receive buffer des criptor point crxbdptr = (sbufferdescriptor *)gcrxbdptr[channel]; // step 3. clear owner to cpu crxbdptr->bufferdataptr &= bownership_cpu ; // step 4. get length and status crxbdptr->lengthfield = rxlength = modeint_rxdatasize[channel] ; crxbdptr->statusfield = inthdlcstatus ; // step 5. get next buffer descriptor gcrxbdptr[channel] = (u32)crxbdptr->nextbufferdescriptor ; // step 6. initialize hdlc dma for receive hdlc_rx_init(channel) ; } else // read received data from hdlc receive fifo entry readdatafromfifo(channel, 15) ; } } // 5. save hdlc receive status if ( inthdlcstatus & ( rxov|rxabt|rxaerr|rxfap|rxfd|rxdcd|rxsdcd|rxidle) ) { // hdlc rx overrun error if ( inthdlcstatus & rxov ) { ghdlcrxstatus[channel].rxoverrun++ ; hstat(channel) |= rxov ; // check all descriptor is used, then enable hdma rx if ( gcrxbdptr[channel] == pcrxbdptr[channel] ) hdlc_rx_init(channel) ; } if ( inthdlcstatus & rxabt ) { ghdlcrxstatus[channel].rxabort++ ; hstat(channel) |= rxabt ; hdlc_rx_init(channel) ; }
ks32c50100/5000a risc microcontroller d iagnostic source code 3- 87 if ( inthdlcstatus & rxaerr ) ghdlcrxstatus[channel].rxaddresserror++ ; if (inthdlcstatus & rxfap) ghdlcrxstatus[channel].rxfifoaddrpresent++ ; if (inthdlcstatus & rxfd) { ghdlcrxstatus[channel].rxflagdetected++ ; hstat(channel) |= rxfd ; } if (inthdlcstatus & rxdcd) ghdlcrxstatus[channel].rxlevelofdcd++ ; if (inthdlcstatus & rxsdcd) { ghdlcrxstatus[channel].rxtransitionofd cd++ ; hstat(channel) |= rxsdcd ; } if (inthdlcstatus & rxidle) { ghdlcrxstatus[channel].rxidle++ ; hstat(channel) |= rxidle ; } } ? ? ? ? in the interrupt service routine for receive operation, store the received frame data, receive frame length, and status. so user program that process received frame, can handle this received frame with buffer descriptor information. the sample code for processing received frame is listed in listing 3-43 . listing 3-43. receivehdlcframe() function for KS32C5000(a) (hdlcinit.c) /* * function : receivehdlcframe * description : receive hdlc frame */ int receivehdlcframe(u32 channel) { sbufferdescriptor *prxbdptr ; u32 crxbdptr ; u32 *databuffer ; u32 length ; u32 status ; // step 1. get current frame buffer pointer crxbdptr = (u32)gcrxbdptr[channel] ; do { // step 2. get frame buffer pointer for process prxbdptr = (sbufferdescriptor *)pcrxbdptr[channel] ; // step 3. check ownership is cpu or not
diagnostic source code ks32c50100/5000a risc microcontroller 3 - 88 if ( !((u32)(prxbdptr->bufferd ataptr) & bownership_dma) ) { // step 4. if ownership is cpu, then receive frame is exist // so, get this frame to process databuffer = (u32 *)prxbdptr->bufferdataptr ; length = prxbdptr->lengthfield ; status = prxbdptr->statusfield ; if ( !( status & (rxferr | drxabt) ) ) { memcpy ((u8 *)&tempbuf,(u8 *)databuffer,length); } } else break ; // step 5. change owner to dma (prxbdptr->bufferdataptr) |= bownership_dma; prxbdptr->lengthfield = (u32)0x0; p rxbdptr->statusfield = (u32)0x0; // step 6. check all descriptor is used, then enable hdlc receive if ( gcrxbdptr[channel] == pcrxbdptr[channel] ) hdlc_rx_init(channel) ; // step 7. get next frame descriptor pointer to process pcrxbdptr[channel] = (u32)(prxbdptr->nextbufferdescriptor) ; } while (crxbdptr != pcrxbdptr[channel]); return 1 ; }
ks32c50100/5000a risc microcontroller d iagnostic source code 3- 89 when you processing the received frame, you can follow this step. step 1. get current frame buffer pointer step 2. get frame buffer pointer for process step 3. check ownership is cpu or not in this step, if the owner is dma, then this buffer can ? t be used. so at the first time, you should check this owner bit. step 4. get the frame to process in this step, you can check received frame by status field in the buffer descriptor, if there is no receive error, then you can get received frame, and process it, but if have any error, then just leave out from receive operation. step 5. change owner to dma after process received frame, cpu should change owner bit to dma, if this bit is not changed, then next hdlc initialize routine can ? t use this frame buffer. step 6. check all descriptor is used, then enable hdlc receive if buffer descriptor is already full, then enable hdlc controller and hdma controller enable to receive incoming frame data. step 7. get next frame descriptor pointer to process the flow of receive and processing the received data is depicted in figure 3-24 , and figure 3-25 .
diagnostic source code ks32c50100/5000a risc microcontroller 3 - 90 exit interrupt service routine frame valid or error ? hdlc interrupt with hdma rx stop rxfifo available receive frame hdlc interrupt with hdlc rxfifo available get current receive buffer descriptor pointer clear owner to cpu get length and status get next buffer descriptor initialize hdlc and hdma for receive incoming frame get received byte count from status register increase received data byte count read received data from hdlc rx fifo to received byte count increase received data byte count (4 word) read received data from hdlc rx fifo to 4 word frame valid or error exit interrupt service routine and wait next data receive [note] in the interrupt mode receive operation rx frame valid or frame error means the last of frame data is received. figure 3-24. hdlc receive flow for KS32C5000(a)
ks32c50100/5000a risc microcontroller d iagnostic source code 3- 91 finished start processing received frame get current buffer descriptor's pointer to process get frame buffer pointer get frame data buffer pointer owner is cpu ? get status and length get frame buffer pointer frame error ? change owner to dma all buffer is used, then enable hdlc and hdma again get next buffer descriptor every received frame is processed ? no yes yes no no finished figure 3-25. hdlc processing received frame flow for KS32C5000(a)
diagnostic source code ks32c50100/5000a risc microcontroller 3 - 92 high-level data link controller for ks32c50100 hdlc diagnostic code function the diagnostic source code for the hdlc (high-level data link controller) is composed of four files, hdlc100.h, hdlc100.c, hdlcinit100.c, and hdlclib100.c. hdlc100.h : definition file for hdlc diagnostic code, register bit value, frame structure, frame descriptor structure, and function prototype. hdlcmain.c : the main diagnos tic code function call for hdlc function test. hdlcinit100.c : initialize hdlc and hdma controller for normal operating environment, each interrupt service routine. hdlclib100.c : the library functions for diagnostic code. snds.h listing 3-46. system control registers (snds.h) #define vprint *(volatile unsigned int *) #define base_addr 0x3ff0000 // system manager register #define syscfg (vprint(base_addr+0x0000) : // gdma 1 : hardware control registers used in the diagnostic c-source code are defined in snds.h header file. in this header file , base_addr has the same value as the base address configured at boot code on the reset time. the address of system configuration register is typically calculated by adding the register ? s offset to base_addr. the base address (reset value = 0x3ff0000) can be changed by writing a new base address to the special register bank base pointer field of the syscfg register. base_addr should be updated before compiling and linking the diagnostic code. a control register should be declared as volatile in order to avoid certain compiler optimizations that prevent the value of variable from being accessed correctly as the expression indicates. for example : volatile int clock; int timer1; timer1 = clock; if(timer1 == clock) ...; if the clock is not declared as volatile , some compilers can optimize the two expressions in such a way that the value of the clock is examined only once.
ks32c50100/5000a risc microcontroller d iagnostic source code 3- 93 definitions for hdlc listing 3-47. new definition for hdlc (hdlc100.h) // hdlc registers #define hmode(channel) (vpint(base_addr+0x7000 + channel*0x1000)) #define hcon(channel) (vpint(base_addr+0x7004 + channel*0x1000)) #define hstat(channel) (vpint(base_addr+0x7008 + channel*0x1000)) #define hinten(channel) (vpint(base_addr+0x700c + channel*0x1000)) #define htxfifoc(channel) (vpint(base_addr+0x7010 + channel*0x1000)) #define htxfifot(channel) (vpint(base_addr+0x7014 + channel*0x1000)) #define hrxfifo(channel) (vpint(base_addr+0x7018 + channel*0x1000)) #define hbrgtc(channel) (vpint(base_addr+0x701c + channel*0x1000)) #define hprmb(channel) (vpint(base_addr+0x7020 + channel*0x1000)) #define hsar0(channel) (vpint(base_addr+0x7024 + channel*0x1000)) #define hsar1(channel) (vpint(base_addr+0x7028 + channel*0x1000)) #define hsar2(channel) (vpint(base_addr+0x702c + channel*0x1000)) #define hsar3(channel) (vpint(base_addr+0x7030 + channel*0x1000)) #define hmask(channel) (vpint(base_addr+ 0x7034 + channel*0x1000)) #define hdmatxptr(channel) (vpint(base_addr+0x7038 + channel*0x1000)) #define hdmarxptr(channel) (vpint(base_addr+0x703c + channel*0x1000)) #define hmflr(channel) (vpint(base_addr+0x7040 + channel*0x1000)) #define hrbsr(channel) (vpint(base_addr+0x7044 + channel*0x1000)) // register bit control macros #define hdlcreset(channel) hcon(channel) |= txrs|rxrs|dtxrs|drxrs ; #define hdlctxen(channel) hcon(channel) |= txen #define hdlcrxen(channel) hcon(channe l) |= rxen #define hdmatxen(channel) hcon(channel) |= dtxen #define hdmarxen(channel) hcon(channel) |= drxen #define hdlcloopbacken(channel) hcon(channel) |= txloop #define hdlcloopbackdis(channel) hcon(channel) &= ~txloop #define drxsizeset(channel,size) hrbsr(channel) = size #define maxframelengthset(channel,size) hmflr(channel) = size #define interclken(channel) hcon(channel) |= dpllen|brgen ; #define hdlctxgo(channel) hdlctxen(channel); hdmatxen(channel) #define hdlctxreset(channel) hcon(channel) |= txrs #define hdlcrxreset(channel) hcon(channel) |= rxrs ; #define hdlcdmatxreset(channel) hcon(channel) |= dtxrs ; #define hdlcdmarxreset(channel) hcon(channel) |= drxrs ; #define showchan(channel) ch=(!channel)?'a':'b' hdlc has two operating mode which are hdma and interrupt. each mode should have the different register setting and the special interrupt service routine. from this after , we will describe on hdma mode operation without special comment. for interrupt mode , we spare the last paragraph of this section and the paragraph of the way to use status register.
diagnostic source code ks32c50100/5000a risc microcontroller 3 - 94 hdlc initialize the hdlc and hdma should be initialized before getting into operation. hdlcinitialize() function is programmed to accomplish this initialization. the following sections describe the contents of this function. the ks32c50100 has hdlc and hdma controller for high-level data link interface. the hdma is used for transferring and receiving data to memory and transfer the transmit data to hdlc. the hdlc can support up to 10mbps and full duplex operation using an external/internal clock. so you need to set the hdlc, and hdma controller to work properly. the detail of hdlc initialize function is described in source code listing 3-48 and figure 3-26 . listing 3-48. hdlcinitialize() function (hdlc100init.c) /* * function : hdlcinitialize * description : this function initialize the hdlc block */ void hdlcinitialize (void) { u8 channel; u32 userarea; for(channel=hdlca;channel<=hdlc b;channel++) { //reset all hdlc block hdlcreset(channel) ; // internal register setting for tx/rx operation hmode(channel) = gmode = nrz | txcbo2 | rxcrxc | brgmclk | txotxc ; hcon(channel) = gcontrol =tx1wd | rx1wd | dtxstsk | drxstsk | rxwa0 | txdtr | brgen; hinten(channel) = ghinten = dtxfdie | drxfdie | drxnlie | drxnoie | rxmovie; hbrgtc(channel) = getbaudrate(hdlcbaud) ; addressset(channel) ; maxframelengthset(channel,maxframedata); hrbsr(channel) = rxbuflength ; // i nitialize buffer descriptor txbd_init(channel) ; rxbd_init(channel) ; txdatawrite(channel) ; // ready to receive data hdmarxen(channel) ; hdlcrxen(channel) ; } // interrupt vector setup syssetinterrupt(nhdlctxa_int, hdlctxa_isr ); syssetinterrupt(nhdlcrxa_int, hdlcrxa_isr ); syssetinterrupt(nhdlctxb_int, hdlctxb_isr ); syssetinterrupt(nhdlcrxb_int, hdlcrxb_isr );
ks32c50100/5000a risc microcontroller d iagnostic source code 3- 95 enable_int(nhdlctxa_int); enable_int(nhdlcrxa_int); enable_int(nhdlctxb_int); enable_int(nhdlcrxb_int); enable_int(n global_int); // initialize global variables } hdlc initialize finished set global hdlc and hdma registers hdma tx buffer descriptor initialize hdma rx buffer descriptor initialize enable hdlc tx, hdma rx interrupt set mac, bdma receive control register hdlc initialize start reset hdlc, hdma controller for each channel , a & b setup hdlc, hdma controller 1) reset hdlc, hdma controller 2) set global hdlc control register brgtc and hrbsr register 3) bdma tx buffer descriptor initialize 4) bdma rx buffer descriptor initialize 5) disable hdlc, hdma tx/rx interrupt 6) enable hdlc tx, hdma rx interrupt we use hdlc tx interrupt for transmit operation, and hdma rx interrupt for receive operation. 7) set hdlc, hdma receive control register figure 3-26. hdlc initialize flow
diagnostic source code ks32c50100/5000a risc microcontroller 3 - 96 the each step of hdlc initializing function is described as followings. step 1 : resettig hdlc and hdma block first of all , it is necessary to reset hdlc and dma controller , which initialize registers as defaults values. see listing 3-47 and listing 3-48. for(channel=hdlca;channel<=hdlcb;channel++) { //reset all hdlc block hdlcreset(channel) ; } step 2 : setting initial condition of hdma and hdlc step 2.1 :selecting the clock mode and clock selection register bit name description example control bit behavior hmode rxclk selecting rx clock rx clock can be selected one of output clock from brg or dplloutr or external txc/rxc pin. rxcrxc external clock to rxc pin is selected as rx clock. txclk selecting tx clock tx clock can be selected one of output clock from brg or dplloutt or external txc/rxc pin. txcbo2 brgout2 clock generated by brg block is selected as tx clock. brgclk internal brg clock for tx/rx clock brg source clock can be select between mclk and rxc pin. if you use a clock derived from brg block as tx/rx clock of hdlc, enable brgen bit in hcon register. note: using register hbrgtc, the frequency of baud rate clock is determined (see step 2.1.1 baud rate generator). brgmclk system main clock selected as brg source clock. dpllclk internal dpll clock for tx/rx clock dpll source clock can be selected among txc/rxc pin, mclk and brgout1, 2 .if you use a clock derived from dpll block as tx/rx clock of hdlc, enable dpllen bit in hcon register. ? not used in diagnostic program. hcon brgen brg enable enable brg counter and start generating brgout1,2 brgen brg counter loads brgtc and counting down for generating brgout1,2 dpllen dpll enable enable dpll and start finding a locking edge in the incoming data. ? not used in diagnostic program.
ks32c50100/5000a risc microcontroller d iagnostic source code 3- 97 register bit name description example control bit behavior hbrgtc cnt0 cnt1 cnt2 see user ? s manual hbrgtc = 0xxxxx; brg counter load this value. hbrgtca = getbaudrate (hdlcbaud); getbaudrate is a function to get brg counter value. simply you pass a value of baudrate as parameter . hmode txcops selecting txc pin as output when txc pin is not the input clock ,you can monitor internal clocks through txc pin. txotxc tx clock is appeared at txc pin. step 2.1.1 baud rate generator you have to set the programmable baud rate generator(brg) to get a desired baud rate. this hbrgtc register contains a 16-bit time constant register, which is made of a 12-bit down counter for time constant value and two control bits to divide by 16 or 32. using the following formula, you can obtain the desired baud rate. brgout1 = (mclk2 or rxc) / (cnt0 +1) / (16 cnt1 ) brgout2 = brgout1 / (1 or 16 or 32 according to cnt2 value of the hbrgtc) by changing cnt2 hbrgtc[1:0] in hbrgtc register , two different brg can be obtained. the getbaudrate() program can get brgtc value as shown in listing 3-48 . this function get the wanted baud rate as close as possible by using internal 50mhz mclk and is only for brgout2 and has no consideration for brgout1. so if you want to use external clock to get baud rate, a slight modification will be needed like changing the defined mclk2 value. listing 3-48. getbaudrate(u32 wantedbr) function (hdlc100lib.c) #define mclk2 25000000 /* * function : getbaudrate * description : hdlc internal time constant value (brgtc) */ u32 getbaudrate(u32 wantedbr) { u32 cnt0,selcnt0,cnt1,cnt2; u32 i,scal1,scal2; float cal cedbr,calcedbr1 ; float diffval1 , diffval2 , seldiffval ; seldiffval = (float) wantedbr; for(i=0;i<6;i++)
diagnostic source code ks32c50100/5000a risc microcontroller 3 - 98 { switch(i) { case 0 : scal1 = 1 ; scal2 = 1 ; break; case 1 : scal1 = 1 ; scal2 = 16 ; break; case 2 : scal1 = 1 ; scal2 = 32 ; break; case 3 : scal1 = 16 ; scal2 = 1 ; break; case 4 : scal1 = 16 ; scal2 = 16 ; break; case 5 : scal1 = 16 ; scal2 = 32 ; break; default : ; } cnt0 = mclk2 / wantedbr / scal1 / scal2 ; if(cnt0==0 | cnt0 > 4096) continue ; calcedb r = (float) mclk2 / (float)cnt0++ / (float)scal1 / (float)scal2; diffval1 = calcedbr-(float)wantedbr ; calcedbr1 = (float) mclk2 / (float)cnt0 / (float)scal1 / (float)scal2; diffval2 = (float)wantedbr-calcedbr1 ; if(diffval1 > diffval2) { diffval1 = diffval2 ; calcedbr = calcedbr1 ; cnt0 -- ; } else cnt0-=2 ; if(diffval1 ks32c50100/5000a risc microcontroller d iagnostic source code 3- 99 brg dpll mclk rxc pin mclk rxd brgtc value brgout1 brgout2 rxc pin txc pin figure 3-27. hdlc internal clock block diagram
diagnostic source code ks32c50100/5000a risc microcontroller 3 - 100 step 2.2 selecting data format/flag pattern/endian mode register bit name description example control bit behavior hmode df selecting data format you can use nrz/nrzi and fm0/fm1/manchester data format provided by ks32c50100 . nrz nrz data format will be used for data encoding/decoding for channel a. txlittle selecting endian mode it is depends on txlittle and rxlittle bits whether data bytes are swapped or not between system bus and hdlc tx/rx fifo. data bytes are swapped in default mode when you set little pin low and txlittle and rxlittle is disabled.(i.e. normal big endian mode) the reason is why tx/rx fifo is little endian mode. (default) the transmitted data will be a big endian format. rxlittle (default) we assume the data which will be received as big endian format. txpl selecting preamble length you can select the length of preamble to be sent before opening flag. ? not used in diagnostic program. hcon txprmb selecting flag pattern when this bit is set to '1' ,your pattern will be transmitted. and this bit must be disabled after tx enabled. if not, the data to be transmitted can not be transmitted. in case txprmb bit is ? 0 ? , flag or mark idle is selected. ? not used in diagnostic program. hprmb preamble pattern [7:0] setting special idle pattern if you want to transmit special idle pattern, you must write this into hprmb (8-bit) register. ? not used in diagnostic program.
ks32c50100/5000a risc microcontroller d iagnostic source code 3- 101 step 2.3 setting the interrupt enable bits you can manage hdlc with best performance, when the interrupt bits are set correctly and interrupt service routines are programmed concisely for your system. these bits can be enabled when txen,rxen,dtxen and drxen are set in hcon register. see listing 3-47 , listing 3-48 and step 6 for(channel=hdlca;channel<=hdlcb;channel++) { // setting interrupt enable hinten(channel) = dtxfdie | drxfdie | drxnlie | drxnoie | rxmovie ; hdmatxen(channel); hdlctxen (channel); } after this statement, hdlc and hdma interrupt can be used. step 2.4 setting station address there are four station address registers and one mask register to recognize address(hsadr0~3 and hmask) each registers consist of 32-bits. the value of bits in hmask represents whether the consistent bits of hsadr0~3 will be compared with the incoming address field. if the address is not matched, the corresponding frame is discarded. listing 3-50 show that if the first 4-bytes of hdlc incoming bit steam is one of 0x1234, 0xabcd, 0xffff and 0xaaaa, it will be accepted as valid address. listing 3-50. addressset(u8 channel) function (hdlc100lib.c) /* * function : addressset * description : hdlc station address */ void addressset(u8 channel) { hsar0(channel) = 0x12345678 ; hsar1(channel) = 0xabcdef01 ; hsar2(channel) = 0xffffffff ; hsar3(channel) = 0xaaaaaaaa ; hmask(channel) = 0xfffff0000; } step 2.5 setting other registers for dma operation there are two 16-bit-long registers which should be set before dma operation. one is hmflr limiting the length of incoming frame data, and the other is hrbsr determining the buffer size of a rx buffer descriptor. if the frame data received exceeds hmflr register value, the frame is discarded and flv(frame length violation) bit is set in the corresponding buffer descriptor. see listing 3-47 and listing 3-48. for(channel=hdlca;channel<=hdlcb;channel++) { //reset all hdlc block maxframelengthset(channel,maxframelength) ; hrbsr(channel) = rxbuflength ; }
diagnostic source code ks32c50100/5000a risc microcontroller 3 - 102 step 3 initializing the hdma tx/rx frame descriptor hdlc uses hdma to receive and transmit frame data. and hdma use a buffer descriptor structure to interface with memory automatically. the transmit hdma frame descriptor has frame buffer pointer, control field, length and status field, and next frame descriptor field, the hdma receive frame descriptor is almost same as transmit frame descriptor except control field. the basic frame descriptor structure is described in listing 3-51, and figure 3-27. listing 3-51. buffer descriptor structure (hdlc100.h) // tx/rx buffer descriptor structure (with previous descriptor) typedef struct bd { u32 bufferdataptr; u32 reserved; // cf: rx-reserved, tx-reserved(25bits) + control bits(7bits) u32 statuslength; struct bd *nextbd ; struct bd *prevbd ; } sbufferdescriptor; frame data pointer #1 next frame descriptor status length prev frame descriptor frame data pointer #2 next frame descriptor status length prev frame descriptor frame data pointer #n next frame descriptor status length prev frame descriptor figure 3-28. hdma buffer descriptor structure
ks32c50100/5000a risc microcontroller d iagnostic source code 3- 103 the hdma tx/rx frame descriptor, and frame buffer area should be non-cacheable, because hdma can update the value, so when we initialize buffer descriptor , oring noncache(= 0x4000000) for non-cacheable access. the listing 3-52 , and listing 3-53 show the detail operation of setup hdma tx/rx frame descriptor. the default owner of transmit hdma frame descriptor is cpu, and the default owner of receive hdma owner is hdma, after receive frame, hdma controller change the owner bit on hdma frame descriptor to cpu owner , then it can be used by cpu. listing 3-52. txbd_init(u8 channel) function (hdlc100init.c) /* * void txbd_init(u8 channel) ; * initialize tx buffer descriptor */ void txbd_init(u8 channel) { sbufferdescriptor *pstxbd ; s bufferdescriptor *psstartbd ; sbufferdescriptor *psprevbd ; u32 txbdatastartaddr ; u32 txbuflength ; u32 i ; u32 misalignbytes ; gctxbdstart[channel] = (u32)stxbdstart[channel] | noncache ; hdmatxptr(channel) = gctxbdstart[channel] ; pstxbd = (sbufferdescriptor *)gctxbdstart[channel] ; psstartbd = pstxbd ; pstxbd->prevbd = (sbufferdescriptor *)null ; txbdatastartaddr = (u32)txbbaseaddr ; txbdatastartaddr |= noncache ; for(i=1; i<=maxtxbdcount; i++){ txbuflength = patterngen(i) & 0x3ff; //debug if(txbuflength<6) txbuflength = 6 ; misalignbytes = (word-txbuflength%word)%word ; pstxbd->bufferdataptr = (u32)txbdatastartaddr & bownership_cpu; pstxbd->reserved = 0x0; pstxbd->statuslength = txbuflength ; //next buffer descriptor allocation if(pstxbd->prevbd != (sbufferdescriptor *) null){ psprevbd->nextbd = pstxbd ; } psprevbd = pstxbd ; pstxbd++ ; if(i!=maxtxbdcount) pstxbd->prevbd = psprevbd ;
diagnostic source code ks32c50100/5000a risc microcontroller 3 - 104 txbdatastar taddr += txbuflength + misalignbytes ; } pstxbd-- ; //assign last buffer descriptor pstxbd->nextbd = psstartbd ; //assign first buffer descriptor psstartbd->prevbd = pstxbd ; } listing 3-53. rxbd_init(u8 channel) function (hdlc100init.c) /* * void rxbd_init(u8 channel) ; * initialize rx buffer descriptor. */ void rxbd_init(u8 channel) { sbufferdescriptor *psrxbd ; sbufferdescriptor *psprevbd, *psstartbd ; u32 rxbdatastartaddr ; u32 i ; //rxbbaseaddra = (u32 *)0x20000 0 ; gcrxbdstart[channel] = (u32)srxbdstart[channel] | noncache ; hdmarxptr(channel) = gcrxbdstart[channel] ; psrxbd = (sbufferdescriptor *)gcrxbdstart[channel] ; psstartbd = psrxbd ; psrxbd->prevbd = (sbufferdescriptor *)null ; rxbdatastartaddr = (u32)rxbbaseaddr[channel] | noncache ; for(i=1; i<=maxrxbdcount; i++){ psrxbd->bufferdataptr =(u32)rxbdatastartaddr | bownership_dma; psrxbd->reserved = 0x0 ; psrxbd->statuslength = 0x0 ; //next buffer descriptor allocatio n if(psrxbd->prevbd != (sbufferdescriptor *) null) psprevbd->nextbd = psrxbd ; psprevbd = psrxbd ; // = psrxbd++ psrxbd++ ; if(i!=maxrxbdcount) psrxbd->prevbd = psprevbd ; rxbdatastartaddr += rxbuflength ; } // psrxbd-- ; //assign last buffer descriptor
ks32c50100/5000a risc microcontroller d iagnostic source code 3- 105 psprevbd->nextbd = psstartbd ; //assign first buffer descriptor psstartbd->prevbd = psrxbd ; } in our diagnostic code , we prepare whole tx buffer data and controls before operating. txdatawrite() program do this as described at listing 3-54. . listing 3-54. txdatawrite(u8 channel) function (hdlc100init.c) /* * void txdatawrite(u8 channel) ; * preparing tx data to send. */ void txdatawrite(u8 channel,int owner) { sbufferdescriptor *pstxbd ; u32 *bufptr ; u32 *pbdptr ; u32 i, j, loop, txlength, misalignbytes; bufptr = (u32 *) ( (u32) txbbaseaddr | noncache ) ; pstxbd = stxbdstart[channel] ; pstxbd = (sbufferdescriptor *) ( (u32) pstxbd | noncache ) ; for(i=0; ibufferdataptr ; if(owner==dma) *pbdptr |= bownership_dma ; pstxbd->reserved = lastbf; txlength = (u32)pstxbd->statuslength & 0xffffff ; misalignbytes = (word-txlength%word)%word ; *bufptr++ = 0xaaaaaaaa ; loop = (txlength<4) ? 0 : txlength/4-1 ; for(j=0; jnextbd ; } }
diagnostic source code ks32c50100/5000a risc microcontroller 3 - 106 step 6 enable interrupt hdma rx and hdlc rx interrupt you can refer transmit and receive operation of hdlc in more detail at hdma rx, and hdlc tx interrupt service routine. see step 2.3. step 7 interrupt vector table setup and enabling interrupt for normal operation, hdlc diagnostic program uses hdlc tx/rx interrupt and hdma(from here on, hdma represents the dma in hdlc). therefore interrupt mode and interrupt service routine should be initialized. there are four interrupt sources for hdlc which are tx/rx interrupts for each a and b channel in ks32c50100. each hdlc interrupt must be enrolled in interrupt vector table to serve the corresponding interrupt event. the interrupt sources are hdlctxa_isr(), hdlcrxa_isr(),hdlctxb_isr() and hdlcrxb_isr(). see listing 3-47 and listing 3-48. see listing 3-55 , figure 3-29, listing 3-56 and figure 3-30 for detail s for hdlc interrupt service hardware flow control hcon register has two bits to manage hardware flow control. txdtr bit directly affects the ndtr pin output state if txen bit is enabled. when txdtr bit is cleared, ndtr goes high. and autoen bit controls the function of ndcd and ncts. the way to use status register there are two kinds of bits in status register. one sort of these bits are cleared automatically when this bit indicating status is cleared. these bits are txfa, txcts, rxfa, rxdcd, rxfv, rxcrc, rxno, rxierr and rxov. and the other bits are cleared by writing ? 1 ? into them using cpu. if many frames are received, the status bits that indicates frame valid or overrun can be set to '1' simultaneously in some case. the previous frame is valid, but cpu does not handle this valid frame yet, and the current frame is come in rx fifo continuously so, rx fifo is full, and rx overrun occurs. the valid frame is moved to memory. in dma mode, if tx underrun bit set to '1', then dma tx abort bit also set to '1'. if rx abort bit or rxoverrun is set to '1', then dma rx abort bit also set to '1'. these bits are cleared by cpu writing '1' it. if tx is enabled, txfa bit is set to '1' in status register. however, it is not set when tx is disabled. when overrun happens, the currently receiving frame is cleared in rxfifo. overrun can happen under two circumstances. in the first case of overrun with frame last byte in rxfifo, the rxov bit is set to '1' along with rxfv of previously received frame. in the second case of overrun without frame last byte in rxfifo, the rxov bit is set to '1' immediately, but the rxfv is not set. the following table show the details on status register. the related bit field means that if status bit field is set , it will be set together normally. and if the affecting bit field is set , the status bit field will meet the setting condition.
ks32c50100/5000a risc microcontroller d iagnostic source code 3- 107 status bit related bit affecting bit setting situation how to use mode how to clear causing interrupt txfa (none) (none) when txfifo is availabe when dma mode , always ? 0 ? i after writing data into tx fifo yes rxfa (none) (none) when rxfifo is availabe when dma mode , always ? 0 ? i after reading data into rx fifo yes txu txfc (none) run out of data during sending resending the underrun frame. d & i writing ? 1 ? yes txcts txabt (none) when ncts pin is low indicate ncts pin state d & i automatic ally no txscts (none) (none) when ncts transit indicate ncts pin transition occured d & i writing ? 1 ? yes dtxabt txu when txu is set when txcts is set to ? 0 ? during transmission. dtxen cleared , so if you want to send another frame , enable dtxen(hcon[6]) bit. d writing ? 1 ? yes txcts dtxfd (none) (none) dma tx operation is done sucessfully. indicate one frame is completed to txfifo. d writing ? 1 ? yes dtxnl (none) (none) when dma tx buffer descriptor pointer has a null list dtxen is cleared. so if you want to send another frame, enable dtxen(hcon[6]) bit. d writing ? 1 ? yes dtxno (none) (none) when dma is not owner of the current buffer descriptor if txstsk(hcon[14]) was set, dtxen is cleared. if drxstsk was not set, always ? 0 ? so if you want to send another frame, enable dtxen(hcon[6]) bit. d writing ? 1 ? yes txfc (none) txu no data in txfifo when meet closing flag an abort is transmitted. indicate that frame transmitting is finished. this bit has no information whether the frame is good or not. d & i writing ? 1 ? yes rxfd (none) (none) when last bit of the flag sequence is received indicate the flag is detected. writing ? 1 ? yes
diagnostic source code ks32c50100/5000a risc microcontroller 3 - 108 rxdcd (none) (none) when ndcd pin is low indicate ndcd pin state d & i automatic ally no rxsdcd (none) (none) when ndcd transit indicate ndcd pin transition occured d & i writing ? 1 ? yes rxfv (none) (none) the last byte of frame is transferred into the last location of the rxfifo and is available to be read signals frame ? s ending boundary to cpu and indicate no frame error. i after reading data into rx fifo yes dpllom (none) (none) when doesn ? t detect an edge in two successive attempt with fm/machester mode when nrz/nrzi mode or dpll disable, always ? 0 ? . you ? d better clear this bit as soon as possible before two miss occur. writing ? 1 ? yes dplltm (none) (none) when doesn ? t detect an edge in two successive attempt with fm/machester mode enter search mode. when nrz/nrzi mode or dpll disable, always ? 0 ? . hdlc can receive an errored data, so we recommand you discard frame. writing ? 1 ? yes rxcrce (none) rxierr frame is completed with crc error d & i automatic ally yes rxno (none) (none) received data is non-octet aligned frame d & i automatic ally yes rxov (none) (none) the received data is transferred into the rxfifo when it is full. a loss of data . continued overruns destroy data in the first fifo register d & i automatic ally yes rxmov (none) (none) no more buffer during receiving data drxen is cleared. d & i writing ? 1 ? yes drxfd (none) (none) dma rx operation is done successfully. d writing ? 1 ? yes drxnl when dma rx buffer descriptor pointer has a null list drxen is cleared and rxfifo is cleared. so if you want to receive another frame , enable drxen(hcon[7]) bit. d writing ? 1 ? yes drxno when dma is not owner of the if drxstsk (hcon[15]) was set, d writing ? 1 ? yes
ks32c50100/5000a risc microcontroller d iagnostic source code 3- 109 current buffer descriptor drxen is cleared. if drxstsk was not set, always ? 0 ? . so if you want to receive another frame, enable drxen (hcon[7]) bit. rxidle (none) (none) 15 more consecutive 1 ? s inactive idle until ? 0 ? is received d & i writing ? 1 ? yes rxabt (none) (none) 7 more consecutive 1 ? s d & i writing ? 1 ? yes rxierr rxno (none) unstable clock discard the received frame d & i automatic ally yes rxcrce note: d: dma mode i: interrupt mode transmit hdlc frame after setting all control register and hdma transmit buffer descriptor, you can transmit packet. if you want to transmit packet, you can follow this step. step 1 get transmit frame descriptor and data pointer get current frame descriptor and data pointer, that will be used for prepare hdlc frame data and transmit control function. step 2 change ownership to hdma because the diagnostic packet of hdlc is ready in buffer data area. you can send this packet by changing ownership to hdma . note: if you want to send a newly generated packet , you should set the control bits , buffer data pointer and lengh at buffer descriptor which you want to send. step 3 enable hdlc and hdma transmit control register to start transmit. step 4 change current frame descriptor to next frame descriptor listing 3-56 shows that sending transmit packet from start buffer descriptor at the amount of lcount after hdma finishing a transmission of a packet , hdlc controller issue hdlc tx interrupt, in this diagnostic code use two hdlc tx interrupt for each channel. the hdlc tx interrupt service routine is only used for check transmit status. the source code for hdlc tx interrupt service routine is described in listing 3-55 .
diagnostic source code ks32c50100/5000a risc microcontroller 3 - 110 listing 3-55. hdlc_tx_isr( ) function (hdlc100init.c) /* * function : hdlc_tx_isr * description : interrupt service routine for hdlc tx */ void hdlctxa_isr(void) { u32 inthdlcstatus ; u32 checkstatus , packetsize; inthdlcst atus = hstata ; clear_pendingbit(nhdlctxa_int) ; if(inthdlcstatus & dtxfd) { ghtxstatus[hdlca].dmatxfd++ ; hstata = inthdlcstatus & dtxfd ; } checkstatus = txscts|txu|dtxabt|dtxnl|dtxno ; if(inthdlcstatus & checkstatus){ if(inthdlcstatus & (dtxno|dtxabt|dtxnl)){ if(inthdlcstatus & dtxabt){ ghtxstatus[hdlca].dmatxabt++ ; hstata = inthdlcstatus & dtxabt ; } if(inthdlcstatus & dtxno){ ghtxstatus[hdlca].dmatxno++ ; hstata = inthdlcstatus & dtxno ; } if(inthdl cstatus & dtxnl){ ghtxstatus[hdlca].dmatxnl++ ; hstata = inthdlcstatus & dtxnl ; } } } if(!checktxstatus(hdlca)) print("\r hdlca tx fail ") ; }
ks32c50100/5000a risc microcontroller d iagnostic source code 3- 111 u32 checktxstatus(u8 channel) { sbufferdescriptor *pstxbdptr ; u32 *pbdptr ; u32 checkhdma ; int i = 0 ; //check tx ownership in all tx bd pstxbdptr = (sbufferdescriptor *) gctxbdstart[channel] ; while(i < maxtxbdcount) pbdptr = (u32 *)&pstxbdptr->bufferdataptr ; checkhdma = (*pbdptr & bownership_dma) ; pb dptr = (u32 *)&pstxbdptr->reserved ; if(*pbdptr & lastbf) { gctxbdend[channel] = (u32) &pstxbdptr->bufferdataptr ; pstxbdptr = (sbufferdescriptor *)gctxbdend[channel] ; gprevtxbdstart[channel] = gctxbdstart[channel] ; gctxbdstart[channel] = (u32) pstxbdptr->nextbd ; //null list pbdptr = (u32 *) &pstxbdptr->statuslength ; //check if transfer is completed checkhdma |= (*pbdptr & txcomp)^txcomp ; // if last bd ownership is dma or tx not completed if (ch eckhdma) return (u32)hdlctx_fail ; else return (u32)hdlctx_ok ; } if (checkhdma) // if hdma ownership is dma return (u32)hdlctx_fail ; else pbdptr = (u32 *)&pstxbdptr->nextbd ; i++ ; } }
diagnostic source code ks32c50100/5000a risc microcontroller 3 - 112 the hdlc frame transmit flow is depicted in figure 3-29 . start transmit packet get the starting tx buffer descriptor pointer and frame buffer pointer change ownership to hdma enable hdlc and hdma transmit change the tx frame descriptor to next frame descriptor [note] if packet is not ready set buffer data pointer set lengh and control [ buffer descriptors to transmit ] get current status & clear pending bit over maxtxbdcount yes check status & status bit clear get first buffer descriptor of current frame no exit hdlc tx interrupt no check owner yes no last buffer descriptor of current frame cpu get next buffer descriptor of current frame hdma fail return tx ok exit hdlc tx interrupt ok check owner and last flag return tx fail hdlc tx interrupt figure 3-29. hdlc frame transmit flow
ks32c50100/5000a risc microcontroller d iagnostic source code 3- 113 receive hdlc frame receive operation of hdlc frame is performed only on the hdma rx interrupt service routine. hdlc rx interrupt is occurred, when a frame reception is finished. you can follow this step to handling hdlc rx interrupt. step 1 clear pending bit of interrupt , get hdlc status and check hdlc status step 2 if hdma rx done , get current descriptor pointer and hdlc status this step is used for get current frame descriptor pointer from hdmarxptr register when hdma rx done. the hdmarxptr register value denote the current processing frame descriptor point or the next frame descriptor pointer. so this value is used for check last received frame or not. step 3 set first buffer descriptor and last buffer descriptor of the current received frame. hdma can consume several buffer descriptors according to the value of hrbsr. so it is needed to check the first and last flag in buffer descriptor. step 4 loop from the first buffer descriptor to last buffer descriptor. this loop is to check one received packet . step 4.1 check ownership of the current buffer descriptor of the received frame. in this step we get the receive frame descriptor pointer to process data, every receive process, use hdma receive frame descriptor pointer. step 4.2 check status at the current buffer descriptor if the current buffer has a status error , this frame will not be moved to memory. so return rx fail. step 4.3 check first and last flag set correctly at the current buffer descriptor if the current buffer has a first and last flag error , this frame will not be moved to memory. so return rx fail. step 4.4 get received buffer data to memory buffer. this step is main function that copy received frame to memory buffer to process. so in the various rtos can announce received frame in this step.
diagnostic source code ks32c50100/5000a risc microcontroller 3 - 114 step 4.4.1 change ownership to hdma at current buffer descriptor change bdma ownership to bdma, because bdma can use this frame descriptor after receive operation. step 4.4.2 clear status and length field at current buffer descriptor step 5 check received frame is valid confirming the chain , by using firstfindbd which return the first buffer descriptor of the received frame. if no error , follow step 6. if not , return rx fail step 6 set first buffer descriptor for a next received frame. when next rx interrupt occured , you can find the first buffer descriptor by setting this with address of step 2 the source code , for the hdlc frame receive operation is described in listing 3-7-14 .
ks32c50100/5000a risc microcontroller d iagnostic source code 3- 115 listing 3-56. hdma_rx_isr() function (hdlcinit.c) /* * function : hdma_rx_isr * description : interrupt service routine for hdma rx * ethenet frame is received in hdma_rx_isr */ void hdlcrxa_isr(void) { u32 inthdlcstatus, prxbdptr ; u32 remainbyte ; inthdlcstatus = hstata ; clear_pendingbit(nhdlcrxa_int) ; if(inthdlcstatus & drxfd){ ghrxstatus[hdlca].dmarxfd++ ; hstata = inthdlcstatus & drxfd ; if(inthdlcstatus & rxcrce) { ghrxstatus[hdlca].rxcrcerr++ ; hstata = inthdlcstatus & drxfd ; } prxbdptr = hdmarxptra ; gframecount[hdlca]++; } if(inthdlcstatus & (rxmov|drxnl|drxno)){ if(inthdlcstatus & rxmov) { ghrxstatus[hdlca].dmarxmov++ ; hstata = inthdlcstatus & rxmov ; print("\r hdlca rx fail") ; return ; } if(inthdlcstatus & drxnl) { ghrxstatus[hdlca].dmarxnl++ ; hstata = inthdlcstatus & drxnl ; print("\r hdlca rx fail"); return ; } if(inthdlcstatus & drxno) { ghrxstatus[hdlca].dmarxno++ ; hstata = inthdlcstatus & rxno ; print("\r hdlca rx fail"); return ; } } if (!checkrxstatushdlc(hdlca, prxbdptr)) print("\r hdlca rx fail") ; }
diagnostic source code ks32c50100/5000a risc microcontroller 3 - 116 /* * function : checkrxstatus * description : in interrupt mode, check rx status */ u32 checkrxstatushdlc(int channel, u32 prxbdptr) { sbufferdescriptor *psrxbdptr; u32 *pbdptr , checkownership , rxstatus , nrxbdptr , framestart = 0xffff0000 ; u32 *first, *last; *crxbdend , *framestartaddr ; nrxbdptr = prxbdptr ; framestartaddr = guserarea[channel] ; while (1) { // 1. get received rx last buffer descriptor psrxbdptr = (sbufferdescriptor *)nrxbdptr ; pbdptr = (u32 *)&psrxbdptr->prevbd ; psrxbdptr = (sbufferdescriptor *)*pbdptr ; pbdptr = (u32 *)&psrxbdptr->bufferdataptr ; crxbdend = pbdptr ; gcrxbdend[channel] = (u32) pbdptr ; first = (u32 *)gcrxbdstart[channel] ; last = (u32 *)nrxbdptr ; psrxbdptr = (sbufferdescriptor *) gcrxbdstart[channel] ; while(psrxbdptr != (sbufferdescriptor *) nrxbdptr) { pbdptr = (u32 *) psrxbdptr ; // 3. check hdma receive ownership checkownership = *pbdptr & bownership_dma ; if (!checkownership)//ownership is cpu rxstatus = (psrxbdptr->statuslength >> 16) & 0xffff; else return (u32)hdlcrx_fail ; if(rxstat us & (cdlost|crce|nonoctet|overrun|abt|flv)) return (u32)hdlcrx_fail ; // 4. check first/last flag in bdrxstatus if((pbdptr!=crxbdend)&(pbdptr!=first)) { if(rxstatus & (framel | framef)) return (u32)hdlcrx_fail ; } else if( pbdptr==first ) { if( !(rxstatus & framef) ) return (u32)hdlcrx_fail ; } else if( pbdptr==crxbdend ) { if( !(rxstatus & framel) ) return (u32)hdlcrx_fail ; } psrxbdptr = psrxbdptr->nextbd ; // to get next buffer
ks32c50100/5000a risc microcontroller d iagnostic source code 3- 117 getrxbddata(channel , u3 2 pbdptr); } ghdlcrxdone = (0x1< diagnostic source code ks32c50100/5000a risc microcontroller 3 - 118 the receive operation in the hdlc rx interrupt service routine is shown in figure 3-30 . hdlc rx interrupt get current status & clear pending bit hdma rx done yes check status & status bit clear get current hdma rx pointer no check owner hdma return rx fail cpu get next buffer descriptor of current frame return rx ok exit hdlc rx interrupt yes check status in buffer descriptor check if first & last flag set correctly get rx buffer data set first buffer descriptor for next frame yes no no set first and last buffer descriptorof current frame figure 3-30. hdlc frame reception flow
ks32c50100/5000a risc microcontroller d iagnostic source code 3- 119 operating on interrupt mode if you want to operate hdlc on interrupt mode , you should initialize registers and interrupt vectors for interrupt mode which is somewhat different from those of hdma. now , we describe only the distinguished point from hdma mode. step 1 remove the bit field related to hdma mode. step 2 set hinten register as interrupt mode for your application ? see the paragraph of the way to use status register. step 3 program the new interrupt service routine for interrupt mode for your application step 4 program the user routine for txenable and environment setting. figure 3-31, and listing 3-57 show the operation flow and the sample program.
diagnostic source code ks32c50100/5000a risc microcontroller 3 - 120 tx interrupt tx fifo available yes yes no no exit hdlc tx interrupt initialize with interrupt mode reset hdlc block register setting interrupt vector setup ready for rx ( rx enable ) ready for tx and start ( tx enable ) end initialization write the data to htxfifoc [move data to txfifo by cpu] last data write the data to htxfifot [move data to txfifo by cpu] clear txfa status bit check status register and do action for your application yes rx interrupt rxfifo available(rxfa) yes no yes exit hdlc tx interrupt rxfifo valid (rxfv) check status register and do action for your application yes read hrxfifo ( 8 word ) [move data to memory by cpu] no figure 3-31. interrupt mode operation flow
ks32c50100/5000a risc microcontroller d iagnostic source code 3- 121 listing 3-57. interrupt mode functions /* * function : hdlcinitialize * description : this function initialize the hdlc block for interrupt mode */ void hdlcinitialize (void) { u8 channel; u32 userarea; for(channel=hdlca;channel<=hdlcb;channel++) { //reset all hdlc block hdlcreset(channel) ; // internal register setting for tx/rx operation hmode(c hannel) = gmode = nrz | txcbo2 | rxcrxc | brgmclk | txotxc ; hcon(channel) = gcontrol = tx1wd|rx1wd|txflag|txdtr | brgen ; hinten(channel) = ghinten = txfcie | txfaie | txuie | rxfaie | rxfvie | rxabtie | rxcrceie | rxnoie | rxovie hbrgtc(channel) = getbaudrate(hdlcbaud) ; addressset(channel) ; hdlcrxen(channel) ; } // interrupt vector setup syssetinterrupt(nhdlctxa_int, hdlctxa_isr ); syssetinterrupt(nhdlcrxa_int, hdlcrxa_isr ); syssetinterrupt(nhdlctxb_int, hdlctxb_isr ); sysset interrupt(nhdlcrxb_int, hdlcrxb_isr ); enable_int(nhdlctxa_int); enable_int(nhdlcrxa_int); enable_int(nhdlctxb_int); enable_int(nhdlcrxb_int); enable_int(nglobal_int); // initialize global variables } /* * function : hdlc_tx_isr * description : interrupt service routine for hdlc tx */ void hdlctxa_isr(void) { if(inthdlcstatus & txfa){ for(i=0; i diagnostic source code ks32c50100/5000a risc microcontroller 3 - 122 for(j=0; j ks32c50100/5000a risc microcontroller d iagnostic source code 3- 123 ghrxstatus[hdlcb].rxcrcerr++ ; *guserarea[hdlcb]++ = 0x0000ffff & hrxfifob ; rxfail = 1 ; } if(inthdlcstatus & rxov) { ghrxstatus[hdlcb].rxoverrun++ ; put_byte('o') ; rxfail = 1 ; } if (rxfail) print("\r hdlcb rx fail") ; } } void cputxago (void) { u32 i ; // setting for diagnostic test gmaxpacketcnt = 20 ; guserarea[hdlcb] = (u32 *)0x 1250000 ; gcpumode = 1 ; // clear user area for(i=0; i<100000; i++) *guserarea[hdlcb]++ = 0x0 ; hmaska = 0x00000000 ; hdlcloopbacken(hdlcb) ; print("\nhdlc cpu mode ch b internal loopback test .... ") ; // tx enable hdlctxen(hdlcb) ; }
diagnostic source code ks32c50100/5000a risc microcontroller 3 - 124 ethernet controller mac diagnostic code function the diagnostic source code for the mac(medium access controller) is composed of four files, mac.h, mac.c, macinit.c, and maclib.c. mac.h: definition file for mac diagnostic code, register bit value, frame structure, frame descriptor structure, and function prototype. mac.c: the main diagnostic code function call for mac function test. macinit.c: initialize mac and bdma controller for normal operating environment, phy configuration, and each interrupt service routine. maclib.c: the library functions for diagnostic code. lan initialize the ethernet controller initialize function is composed of configure phy device, get mac h/w address from iic eeprom, and initialize mac, bdma controller. the configuration of phy device is performed by mii station management function. this function is provided by mac controller special function. the configuration method of phy device is something different between each vendor, in this diagnostic code use only simple code for configure phy, 10/100mbps, and full/half duplex mode. the mac controller has mac h/w address, this address is unique address for each mac, so you need to set the mac h/w address for each mac. in snds and snds100 board use iic eeprom to store mac h/w address. the KS32C5000(a)/ks32c50100 has mac and bdma controller for ethernet interface. the bdma is used for transfer receive data to memory and transfer the transmit data to mac. the mac can support 10/100mbps and full/half duplex mode, so you need to set the mac, and bdma controller to work as your purpose. the detail of lan initialize function is described in source code listing 3-58 and figure 3-32 . listing 3-58. laninitialize() function (macinit.c) /* * void laninitialize(void) */ void laninitialize(void) { // reset the phy chip and start auto-negotiat resetphychip() ; // read mac address from iic eeprom getmymacaddr() ; // initialize mac and bdma controller macinitialize() ; }
ks32c50100/5000a risc microcontroller d iagnostic source code 3- 125 lan initialize start reset phy device get mac h/w address disable mac, bdma interrupt setup mac, bdma interrupt vector reset mac, bdma controller set global mac control register and bdma register bdma tx frame descriptor initialize bdma rx frame descriptor initialize set cam memory and cam control register to filtering incomming message enable mac tx, bdma rx interrupt set mac, bdma receive control register lan initialize finished 1. reset phy device and configure via mii station management control function 2. get mac h/w unique address stored on iic eeprom 3. setup mac, bdma controller 1) disable mac, bdma tx/rx interrupt 2) setup mac, bdma interrupt vector 3) reset mac, bdma controller 4) set global mac control register and bdmalsz register 5) bdma tx frame descriptor initialize 6) bdma rx frame descriptor initialize 7) set cam memory and control register to filtering incomming message 8) enable mac tx, bdma rx interrupt we use mac tx interrupt for transmit operation, and bdma rx interrupt for receive operation. 9) set mac, bdma receive control register figure 3-32. lan initialize flow
diagnostic source code ks32c50100/5000a risc microcontroller 3 - 126 1. reset and configure phy device the station management operation is used to control phy. the phy has many control and status registers. mac can control phy, and it can read the phy status. phy has a unique address, and there is many address for phy internal control and status register. the operation of read, and write to the station management register is described in below. and the source code for station management register read and write function is described in listing 3-59 . mii station management read operation step 1. specify the phy address and a phy internal register address in the stacon register step 2. set busy bit in stacon, then a phy read operation is started. step 3. check busy bit in stacon, after read operation is finished, this bit is cleared. step 4. read stadata, the stadata register has the value of the phy station register. mii station management write operation step 1. write the station management data to stadata register. step 2. specify the phy address, and a phy internal register address in stacon. step 3. set write, and busy bit in stacon, then phy write operation is started. step 4. check busy bit in stacon, when the write operation is finished, this bit is cleared. listing 3-59. miistationread(), miistationwrite() function (macinit.c) /* * function : miistationread, miistationwrite * description : mii interface station management register read or write * input : phyinaddr(phy internal register address) * phyaddr(phy unique address) * phywrdata(when write) * output: phyrddata(whenread) */ void miistationwrite(u32 phyinaddr, u32 phyaddr, u32 phywrdata) { stadata = phywrdata ; stacon = phyinaddr | phyaddr | miibusy | phyregwrite ; while( (stacon & miibusy) ) ; delay_physet() ; } u32 miistationread(u32 phyinaddr, u32 phyaddr) { u32 phyrddata ; stacon = phyinaddr | phyaddr | miibusy ; while( (stacon & miibusy) ) ; phyrddata = stadata ; return phyrddata ; } the sample code for configuring the phy device is
ks32c50100/5000a risc microcontroller d iagnostic source code 3- 127 listing 3-60. resetphychip() function (macinit.c) /* * function : resetphychip * description : reset the phychip, auto-negotiation enable */ void resetphychip(void) { //miistationwrite(phy_cntl_reg, phyhwaddr, enable_an | restart_an); // auto-negotion enable //miistationwrite(phy _cntl_reg,phyhwaddr, 0x0) ; // 10mbps, half-duplex mode //miistationwrite(phy_cntl_reg,phyhwaddr,phy_fullduplex) ; // 10mbps, full-duplex mode //miistationwrite(phy_cntl_reg,phyhwaddr,dr_100mb) ; // 100mbps, half-duplex miistationwrite(phy_cntl_reg,phyhwaddr,dr_100mb|phy_fullduplex) ; // 100mbps, full- duplex mode gduplexvalue = fulldup ; // this variable shouldbe set when use full-duplex mode. } 2. get unique h/w mac address the every mac has unique h/w address, this is used when filtering incoming message from network. the cam is used for filtering incoming message address. in snds and snds100 use iic eeprom for store mac h/w address for system. listing 3-61. getmymacaddr() function (macinit.c) /* * function : getmymacaddr * description : get mac address from iic eeprom */ void getmymacaddr(void) { u8 *macaddr; u8 tempaddr[mac_addr_size]; int i; gcam0_addr0 = gcam0_addr1 = 0 ; #if mac_addr_from_iic_eeprom // when use iic eeprom for store mac address macaddr=(u8 *)iicreadint((u8)iic_dev_0,(u32)imacaddrptr,(u32)mac_addr_size) ; #else // when manual ly setting the mac address macaddr[0] = 0x00 ; macaddr[1] = 0x00 ; macaddr[2] = 0xf0 ; macaddr[3] = 0x11 ; macaddr[4] = 0x00 ; macaddr[5] = 0x00 ; #endif /* get mac address */
diagnostic source code ks32c50100/5000a risc microcontroller 3 - 128 for (i=0;i<(int)mac_addr_size;i++) tempaddr[i] = *macaddr++; /* copy mac address to global variable */ for (i=0;i<(int)mac_addr_size-2;i++) gcam0_addr0 = (gcam0_addr0 << 8) | tempaddr[i] ; for (i=(int)(mac_a ddr_size-2);i<(int)mac_addr_size;i++) gcam0_addr1 = (gcam0_addr1 << 8) | tempaddr[i] ; gcam0_addr1 = (gcam0_addr1 << 16) ; /* set cam0 register : 0x9100~0x9103, 0x9104, 0x9105 */ cam_reg(0) = gcam0_addr0; cam_reg(1) = gcam0_addr1; for (i=0;i<(int)mac_addr_size;i++) mymacsrcaddr[i] = tempaddr[i]; } 3. setup mac, bdma controller this function is used for setup mac and bdma controller register and interrupt service routine for receive and transmit. the main function for setup mac, and bdma controller is described in listing 3-62 . listing 3-62. macinitialize() function (macinit.c) /* * void macinitialize(void) * initialize mac and bdma controller */ void macinitialize(void) { /*-----------------------------------------------------------------* * 1. disable mac and bdma interrupts. * *-----------------------------------------------------------------*/ disable_int(nmac_rx_int) ; // disable mac rx interrupt disable_int(nmac_tx_int) ; // disable mac tx interr upt disable_int(nbdma_rx_int) ; // disable bdma rx interrupt disable_int(nbdma_tx_int) ; // disable bdma tx interrupt /*-----------------------------------------------------------------* * 2. bdma and mac interrupt vector setup. * *-----------------------------------------------------------------*/ syssetinterrupt(nmac_rx_int, mac_rx_isr) ; syssetinterrupt(nmac_tx_int, mac_tx_isr) ; syssetinterrupt(nbdma_rx_int, bdma_rx_isr) ; syssetinterrupt(nbdma_tx_int, bdma_tx_isr) ; /*--- --------------------------------------------------------------* * 3. set the initial condition of the bdma, and mac * *-----------------------------------------------------------------*/ bdmarxcon = brxrs ; // reset bdmac receiver
ks32c50100/5000a risc microcontroller d iagnostic source code 3- 129 bdmatxcon = btxrs ; // reset bdmac transceiver maccon = swreset ; bdmarxlsz = maxrxframesize ; // 1520 maccon = gmaccon ; /*-----------------------------------------------------------------* * 4. set the bdma tx/rx frame descriptor * *-----------------------------------------------------------------*/ txfdinitialize() ; rxfdinitialize() ; /*-----------------------------------------------------------------* * 5. set the cam control register and the mac address value * *-----------------------------------------------------------------*/ // cam0 register of cam registers : 0x9100~0x9103, 0x9104, 0x9105 cam_reg(0) = gcam0_addr0 ; cam_reg(1) = gcam0_addr1 ; // cam enable register(camen) camen = 0x0001 ; camcon = gcamcon ; /*-----------------------------------------------------------------* * 6. enable interrupt bdma rx and mac tx interrupt. * *-----------------------------------------------------------------*/ enable_int(nbdma_rx_int); enable_int(nmac_tx_int); /*-----------------------------------------------------------------* * 7. configure the bdma and mac control registers. * *-----------------------------------------------------------------*/ readymactx() ; readymacrx() ; } the each step of mac initialize function is described in below. step 1 disable mac and bdma interrupt disable mac, bdma tx/rx interrupt to avoid abnormal branch. step 2 bdma and mac interrupt vector setup interrupt vector setup for mac, and bdma interrupt, after this statement, mac, and bdma interrupt can be used. step 3 set the initial condition of bdma and mac reset the mac controller and bdma controller. and set the duplex mode and interface mode to maccon register. ethernet interface can be configured as mii interface or old style 7-wire interface. the 7-wire interface can be set by mii-off bit.
diagnostic source code ks32c50100/5000a risc microcontroller 3 - 130 step 4 set the bdma tx/rx frame descriptor bdma frame descriptor is used for control bdma automatically. the transmit bdma frame descriptor has frame buffer pointer, control field, length and status field, and next frame descriptor field, the bdma receive frame descriptor is almost same as transmit frame descriptor except control field. the frame descriptor structure is described in listing 3-63 , and figure 3-33 . listing 3-63. frame descriptor structure (mac.h) // tx/rx common descriptor structure typedef struct framedescriptor { u32 framedataptr; u32 reserved; // cf: rx-reserved, tx-reserved(25bits) + control bits(7bits) u32 statusandframelength; u32 nextframedescriptor; } sframedescriptor; frame data pointer #1 next frame descriptor status length frame data pointer #1 next frame descriptor status length frame data pointer #1 next frame descriptor status length figure 3-33. bdma frame descriptor structure the bdma tx/rx frame descriptor, and frame buffer area should be non-cacheable, because bdma can update the value, so when we initialize frame descriptor, add 0x4000000 for non-cacheable access. the listing 3-64 , and listing 3-65 show the detail operation of initialize bdma tx/rx frame descriptor. the default owner of transmit bdma frame descriptor is cpu, and the default owner of receive bdma owner is bdma, after receive frame, bdma controller change the owner bit on bdma frame descriptor to cpu owner, then it can be used by cpu.
ks32c50100/5000a risc microcontroller d iagnostic source code 3- 131 listing 3-64. txfdinitialize() function (macinit.c) /* * void txfdinitialize(void) ; * initialize tx frame descriptor area-buffers. */ void txfdinitialize(void) { sframedescriptor *pframedescriptor; sframedescriptor *pstartframedescriptor; sframedescriptor *plastframedescriptor = null; u32 framedataaddr; u32 i; // get frame descriptor's base address. // +0x4000000 is for setting this area to non-cacheable area. bdmatxptr = (u32)txfdbaseaddr + 0x4000000; gwtxfdptr = gctxfdptr = bdmatxptr; // get transmit buffer base address. framedataaddr = (u32)txfbabaseaddr + 0x4000000; // generate linked list. p framedescriptor = (sframedescriptor *) gctxfdptr; pstartframedescriptor = pframedescriptor; for(i=0; i < maxtxframedescriptors; i++) { if(plastframedescriptor == null) plastframedescriptor = pframedescriptor; else plastframedescriptor->nextframedescriptor = (u32)pframedescriptor; pframedescriptor->framedataptr = (u32)(framedataaddr & fownership_cpu); pframedescriptor->reserved = (u32)0x0; pframedescriptor->statusandframelength = (u32)0x0; pframedescriptor->nextframedescriptor = nul l; plastframedescriptor = pframedescriptor; pframedescriptor++; framedataaddr += sizeof(smacframe); } // end for loop // make frame descriptor to ring buffer type. pframedescriptor--; pframedescriptor->nextframedescriptor = (u32)pstartframedescriptor; }
diagnostic source code ks32c50100/5000a risc microcontroller 3 - 132 listing 3-65. rxfdinitialize() function (macinit.c) /* * void rxfdinitialize(void) ; * initialize rx frame descriptor area-buffers. */ void rxfdinitialize(void) { sframedescriptor *pframedescriptor; sframedescriptor *pst artframedescriptor; sframedescriptor *plastframedescriptor = null; u32 framedataaddr; u32 i; // get frame descriptor's base address. // +0x4000000 is for setting this area to non-cacheable area. bdmarxptr = (u32)rxfdbaseaddr + 0x4000000; gcrxfdptr = bdmarxptr; // get transmit buffer base address. framedataaddr = (u32)rxfbabaseaddr + 0x4000000; // generate linked list. pframedescriptor = (sframedescriptor *) gcrxfdptr; pstartframedescriptor = pframedescriptor; for(i=0; i < maxrxframe descriptors; i++) { if(plastframedescriptor == null) plastframedescriptor = pframedescriptor; else plastframedescriptor->nextframedescriptor = (u32)pframedescriptor; pframedescriptor->framedataptr = (u32)(framedataaddr | fownership_bdma | 0x4000000 ); pframedescriptor->reserved = (u32)0x0; pframedescriptor->statusandframelength = (u32)0x0; pframedescriptor->nextframedescriptor = null; plastframedescriptor = pframedescriptor; pframedescriptor++; framedataaddr += sizeof(smacframe ); } // end for loop // make frame descriptor to ring buffer type. pframedescriptor--; pframedescriptor->nextframedescriptor = (u32)pstartframedescriptor; }
ks32c50100/5000a risc microcontroller d iagnostic source code 3- 133 step 5 set the cam control register and the mac address value cam is used for filtering received frame from other frames. the KS32C5000(a)/ks32c50100 has 21 cam, but in the diagnostic code uses only 1 cam. in diagnostic code for snds and snds100 use iic eeprom for store mac h/w address. so before enable the receive operation, we should load the mac address to cam, and set the value of cam enable/control register. the step 5 doing this operation. step 6 enable interrupt bdma rx and mac tx interrupt in our diagnostic code, we only use bdma rx interrupt for receive operation, and mac tx interrupt for transmit operation. you can refer transmit and receive operation of ethernet controller for more detail of bdma rx, and mac tx interrupt service routine. step 7 configure the bdma and mac control registers this step, prepare all bdma and mac control register to operate. after this set of bdmarxcon, and macrxcon, ethernet controller can receive incoming frame. the value for mac and bdma basic operation is described in table 3-6 .
diagnostic source code ks32c50100/5000a risc microcontroller 3 - 134 table 3-6. mac and bdma control register set value register name function control bit description maccon mac global control register fulldup* full-duplex mode set mii-off* 7-wire or mii interface set mactxcon mac transmit control register encomp interrupt when mac tx is completed or discarded macrxcon mac receive control register rxen mac receive enable stripcrc check the crc, but strip the from message bdmatxcon bdma transmit control register btxbrst bdma transmit burst size(16words) btxmsl110 bdma tx to mac tx start level(6/8) btxstsko bdma tx stop when met not ownered frame bdmarxcon bdma receive control register brxdie interrupt on every received frame brxen bdma receive enable brxlittle received data is stored in little-endian mode (used when little-endian is selected) brxbig received data is stored in big-endian mode (used when big-endian is selected) brxmainc received data is stored in memory address increment brxbrst bdma rx burst size(16words) brxnlie bdma rx null list interrupt enable brxnoie bdma rx not owner interrupt enable brxstsko bdma rx stop when met not ownered frame the source code for setup mac and bdma control register is shown in listing 3-66, listing 3-67 .
ks32c50100/5000a risc microcontroller d iagnostic source code 3- 135 listing 3-66. global variable for mac and bdma control register (macinit.c) // global variables used for mac driver volatile u32 gmaccon = fulldup ; volatile u32 gmactxcon = encomp ; volatile u32 gmacrxcon = rxen | stripcrc ; volatile u32 gbdmatxcon = btxbrst | btxmsl110 | btxstsko ; #ifdef little volatile u32 gbdmarxcon = brxdie | brxen | brxlittle | brxmainc | brxbrst | \ brxnlie | brxnoie | brxstsko ; #else volatile u32 gbdmarxcon = brxdie | brxen | brxbig | brxmainc | brxbrst | \ brxnlie | brxnoie | brxstsko ; #endif volatile u32 gcamcon = compen| broadacc; listing 3-67. readymactx() and readymacrx() function (macinit.c) /* * function : readymactx * description : set tx registers related with bdma & mac to transmit * packet. */ void readymactx(void) { bdmatxcon = gbdmatxcon ; mactxcon = gmactxcon ; } /* * function : readymacrx * description : set rx registers related with bdma & mac to receive packet. */ void readymacrx(void) { bdmarxcon = gbdmarxcon ; macrxcon = gmacrxcon ; }
diagnostic source code ks32c50100/5000a risc microcontroller 3 - 136 transmit ethernet frame after set all control register, and bdma transmit frame descriptor, we are ready to transmit packet. when transmit packet, you can follow this step. step 1 get transmit frame descriptor and data pointer get current frame descriptor and data pointer, that will be used for prepare ethernet frame data and transmit control function. step 2 check bdma ownership check bdma owner is cpu or not, when bdma owner is cpu, cpu can be write control bit, and frame data. if owner is bdma then exit send packet function. step 3 prepare tx frame data to frame buffer copy ethernet frame data to bdma frame buffer, this pointer is pointed by frame data field on frame descriptor. step 4 set tx frame flag and length field. after copy ethernet frame to bdma frame buffer, cpu write control bit and the length of frame data. step 5 change ownership to bdma when ownership is bdma, bdma can work, so after prepare transmit frame descriptor and frame data ownership changed to bdma owner. step 6 enable mac and bdma transmit control register to start transmit. step 7 change current frame descriptor to next frame descriptor the source code for transmit packet is described in listing 3-68 . after transmit ethernet frame mac controller issue mac tx interrupt, in this diagnostic code only use mac tx interrupt for transmit. the mac tx interrupt service routine is only used for check transmit status. the source code for mac tx interrupt service routine is described in listing 3-69 . listing 3-68. sendpacket( ) function (macinit.c) /* * function : sendpacket * description : send ethernet frame function * input : frame data pointer, frame length * output : transmit ok(1) or error(0) */ int sendpacket(u8 *data,int size) { sframedescriptor *pstxfd; u32 *pframedataptr ; u8 *pframedata ; int framelength ; // 1. get tx frame descriptor & data pointer
ks32c50100/5000a risc microcontroller d iagnostic source code 3- 137 pstxfd = (sframedescriptor *)gwtxfdptr ; pframedata = (u8 *)pstxfd->framedataptr ; pframedataptr = (u32 *)&pstxfd->framedataptr; framelength = size + sizeof(etheader) ; // 2. check bdma ownership if ( (*pframedataptr & fownership_bdma) ) return 0 ; // 3. prepare tx frame data to frame buffer memcpy ((u8 *)pframedata,(u8 *)data,framelength); // 4. set tx frame flag & length field #ifdef little pstxfd->reserved = (paddingmode | crcmode | sourceaddrincrement | \ littleendian | widgetalign00 | mactxinten); #else pstxfd->reserved = (paddingmode | crcmode | sourceaddrincrement | \ bigendian | widgetalign00 | mactxinten); #endif pstxfd->statusandframelength = (u32)(framelength & 0xffff); // 5. cheange ownership to bdma pstxfd->framedataptr |= fownership_bdma; // 6. enable mac and bdma tx control register mactxgo(); // 7. change the tx frame descriptor for next use gwtxfdptr = (u32)(pstxfd->nextframedescriptor); return 1 ; } listing 3-69. mac_tx_isr() function (macinit.c) /* * function : mac_tx_isr * description : interrupt service routine for mac tx */ void mac_tx_isr(void) { sframedescriptor *ptxfdptr; u32 *pframedataptr ; u32 status ; u32 ctxptr ; ctxptr = bdmatxpt r ; while ( gctxfdptr != ctxptr ) ptxfdptr = (sframedescriptor *) gctxfdptr;
diagnostic source code ks32c50100/5000a risc microcontroller 3 - 138 // check cpu ownership // if owner is bdma then break pframedataptr = (u32 *)&ptxfdptr->framedataptr; if ( (*pframedataptr & fownership_bdma) ) break ; status = (ptxfdptr->statusandframelength >> 16) & 0xffff; if (status & comp) gsmactxstatus.mactxgood++ ; else { // save error status // check each status, because, error can duplicated if (status & under) gsmactxstatus.undererr++ ; if (status & excoll) gsmactxstatus.excollerr++ ; if (status & txdeffer) gsmactxstatus.txdefferederr++ ; if (status & paused) gsmactxstatus.spaused++ ; if (status & defer) gsmactxstatus.defererr++ ; if (status & ncarr) gsmactxstatus.ncarrerr++ ; if (status & sqerr) gsmactxstatus.ssqe++ ; if (status & latecoll) gsmactxstatus.latecollerr++ ; if (status & txpar) gsmactxstatus.txparerr++ ; if (status & txhalted) gsmactxstatus.stxhalted++ ; // set mac/bdma tx control register for next use. macdebugstatus() ; readymactx() ; } // end if // clear framedata pointer already used. ptxfdptr->statusandframelength = (u32)0x0; gctxfdptr = (u32)ptxfdptr->nextframedescriptor ; } // end while loop mactxdoneflagforloopbackcheck = 1 ; }
ks32c50100/5000a risc microcontroller d iagnostic source code 3- 139 the ethernet frame transmit flow is depicted in figure 3-34 . exit sendpacket() get tx frame descriptor pointer and frame buffer pointer copy frame data to frame buffer check bdma ownership set bdma control field and frame length change ownership to bdma enable mac and bdma transmit change the tx frame descriptor to next frame descriptor mac tx interrupt get current frame descriptor pointer from bdmatxptr compare gctxfdptr and current frame descriptor gctxfdptr get current frame buffer pointer check ownership get next frame descriptor check tx status save good frame status process error status exit mac tx interrupt service routine bdma owner cpu owner compare finished owneship is bdma error call sendpacket() function to transmit packet figure 3-34. ethernet frame transmit flow
diagnostic source code ks32c50100/5000a risc microcontroller 3 - 140 control frame transmit you can transmit a control frame for a remote pause operation in full-duplex mode operation. KS32C5000(a)/ks32c50100 ethernet controller has a function of transmitting and receiving control frame. when transmit control frame, follow this step. the source code is described in listing 3-70 . step 1. set destination address to cam #0 step 2. set source address to cam #1 step 3. set length or type field, op-code, and operand to cam #18 step 4. set zero to double word that proceed cam #18. step 5. enable cam location by camen register. step 6. enable transmit control frame by set the sendpause bit in mactxcon register. step 7. wait control frame transmit is finished. listing 3-70. controlframetransfer() function (macinit.c) /* * function : controlframetransfer * description : transfer control frame data to another host */ void controlframetransfer(void) { char transferpacket ; gbdmatxcon |= btxcpie ; readymactx() ; do { print("\r $$ select transmit(t) or quit(q) ? ") ; transferpacket = get_byte() ; if ( (transferpacket == 't') || (transferpacket == 't') ) { // step 1. set destination a ddress to cam #0 // step 2. set source address to cam #1 // cam #0 : 0000f0110000 (destin addr) // cam #1 : 11f000000000 (source addr) vpint(cam_baseaddr) = 0x0000f011 ; vpint(cam_baseaddr + 0x4) = 0x000011f0 ; vpint(cam_baseaddr + 0x8) = 0x00000000 ; // step 3. set length or type field, opcode, and operand to cam #18 // cam #18 : opcode & operand // cam #18 : pause count value vpint(cam_baseaddr + 0x6c) = 0x88080001 ; // step 4. set to zero proceed cam #18 // cam #19 - #20 : f illed with zero vpint(cam_baseaddr + 0x70) = 0x12340000 ; vpint(cam_baseaddr + 0x74) = 0x00000000 ; vpint(cam_baseaddr + 0x78) = 0x00000000 ;
ks32c50100/5000a risc microcontroller d iagnostic source code 3- 141 vpint(cam_baseaddr + 0x7c) = 0x00000000 ; // step 5. enable cam location // cam enable camen = 0x1c0003 ; // step 6. enable transmit control frame by // set sendpause bit in mactxcon mactxcon |= sdpause | txen ; // step 7. wait control frame finished while ( (bdmastat & s_btxccp) ) ; } } while ( (transferpacket != 'q') && (transferpacket != 'q') ) ; }
diagnostic source code ks32c50100/5000a risc microcontroller 3 - 142 receive ethernet frame receive operation of ethernet frame is performed only on the bdma rx interrupt service routine. a bdma rx interrupt is occurred, when a frame reception is finished. the detail ethernet frame reception operation, follow this step. step 1 : get current frame descriptor pointer and bdma status this step is used for get current frame descriptor ? s pointer from bdmarxptr register. the bdmarxptr register value denote the current processing frame descriptor point or the next frame descriptor pointer. so this value is used for check last received frame or not. step 2 : clear bdma status register bit by write 1. the bdma status, every received frame(brxrdf) bit is cleared by write 1 to bdmastat register, so after receive this interrupt , this bit should be cleared. step 3 : check null list interrupt null list interrupt means, bdmarxptr has 0x00000000 value, this value is not accepted, so when we met this interrupt, we should initialize mac, and bdma controller again. step 4 : get rx frame descriptor in this step, we get receive frame descriptor ? s pointer to process data, every receive process, use bdma receive frame descriptor pointer. step 5 : check received frame is valid or not check received frame descriptor status field to check received frame is valid or not. step 6 : get received frame to memory buffer this step is main function that copy received frame to memory buffer to process. so in the various rtos can announce received frame in this step. step 7 : check received frame has error or not in this step check received frame descriptor status field, to check this frame has error or not. step 8 : change ownership to bdma change bdma ownership to bdma, because bdma can use this frame descriptor after receive operation. step 9 : get next frame descriptor pointer to process when enter bdma receive interrupt service routine, we process all received frame before receive interrupt.
ks32c50100/5000a risc microcontroller d iagnostic source code 3- 143 step 10 : check bdma notowner status bit in the bdmastat register this notowner bit means all bdma frame descriptor is used, so we need set mac and bdma control register to receive frame normally. the source code, for the ethernet frame receive operation is described in listing 3-71 . in the source code, the pre-defined statement, ? KS32C5000_bug_fetch ? is used for KS32C5000 ethernet controller bug fetch routine. at the end of ethernet controller description, we describe more detail for the ethernet controller bug in the KS32C5000. listing 3-71. bdma_rx_isr() function (macinit.c) /* * function : bdma_rx_isr * description : interrupt service routine for bdma rx * ethenet frame is received in bdma_rx_isr */ void bdma_rx_isr(void) { sframedescriptor *prxfdptr ; u32 rxstatus, framelength ; u32 crxptr; u32 sbdmastat ; u8 *pframedata ; #if KS32C5000_bug_fetch u32 fstdata,fstdatasave,*fstframedata ; #endif // step 1. get current frame descriptor and status crxptr = bdmarxptr ; sbdmastat = bdmastat ; // step 2. clear bdma status register bit by write 1 bdmastat |= s_brxrdf ; gsbdmarx status.bdmarxcnt++ ; do { // step 3. check null list interrupt if ( bdmastat & s_brxnl ) { bdmastat |= s_brxnl ; gsbdmarxstatus.brxnlerr++ ; macinitialize() ; break ; } // step 4. get rx frame descriptor prxfdptr = (sframedescriptor *)gcrxfdptr ; rxstatus = (prxfdptr->statusandframelength >> 16) & 0xffff; // step 5. if rx frame is good, then process received frame if(rxstatus & rxgood) { framelength = prxfdptr->statusandframelength & 0xffff ;
diagnostic source code ks32c50100/5000a risc microcontroller 3 - 144 pframedata = (u8 *)prxfdpt r->framedataptr ; gsbdmarxstatus.bdmarxgood++ ; if ( !(gsbdmarxstatus.bdmarxgood%10000) ) print("", tm0.tm_sec,gsbdmarxstatus.bdmarxgood) ; #if KS32C5000_bug_fetch fstframedata = (u32 *)prxfdptr->framedataptr ; fstdatasave = *fstframedata ; fstdata = ( (fstdatasave<<24) & 0xff000000 ) |\ ( (fstdatasave<<8) & 0x00ff0000 ) |\ ( (fstdatasave>>24) & 0x000000ff ) |\ ( (fstdatasave>>8) & 0x0000ff00 ) ; if (gpreviousstatusfield == fstdata) pframedata = pframedata + 4 ; #endif // step 6. get received frame to memory buffer getrxframedata(pframedata, framelength, rxstatus) ; } else { // step 7. if rx frame has error, then process error frame gerrorpacketcnt++ ; // save error status // check each status, because, error can duplicated if (rxstatus & ovmax) gsmacrxstatus.ovmaxsize++ ; if (rxstatus & ctlrecd) gsmacrxstatus.sctlrecd++ ; if (rxstatus & rx10stat) gsmacrxstatus.srx10stat++ ; if (rxstatus & align err) gsmacrxstatus.allgnerr++ ; if (rxstatus & crcerr) gsmacrxstatus.scrcerr++ ; if (rxstatus & overflow) gsmacrxstatus.overflowerr++ ; if (rxstatus & longerr) gsmacrxstatus.slongerr++ ; if (rxstatus & rxpar) gsmacrxstatus.rxparerr++ ; if (rxstatus & rxhalted) gsmacrxstatus.srxhalted++ ; } // step 8. change ownership to bdma for next use (prxfdptr->framedataptr) |= fownership_bdma; // save current status and frame length field, and clear #if KS32C5000_bug_fetch gpreviousstatusfie ld = prxfdptr->statusandframelength ; #endif prxfdptr->statusandframelength = (u32)0x0; // step 9. get next frame descriptor pointer to process gcrxfdptr = (u32)(prxfdptr->nextframedescriptor) ; } while (crxptr != gcrxfdptr); // step 10. check notowner status if ( sbdmastat & s_brxno ) {
ks32c50100/5000a risc microcontroller d iagnostic source code 3- 145 bdmastat |= s_brxno ; gsbdmarxstatus.brxnoerr++ ; readymacrx() ; } bdmarxdoneflagforloopbackcheck = 1 ; // only used for loopback test }
diagnostic source code ks32c50100/5000a risc microcontroller 3 - 146 the receive operation in the bdma rx interrupt service routine is described in figure 3-35 . bdma rx interrupt serviceroutine exit bdma rx interrupt service routine get current frame descriptor (crxptr) and bdma status clear bdma status register by write 1 get received frame to memory buffer (this function is main routine of process the received frame) check null get receive rx frame descriptor check received frame status change ownership to bdma get next frame descriptor pointer to next process check end of receive frame check not owner status no no error all received frame is processed not asserted clear status and macinitialize process error status clear status, and ready receive frame figure 3-35. ethernet frame reception flow
ks32c50100/5000a risc microcontroller d iagnostic source code 3- 147 KS32C5000 ethernet controller bug fetch KS32C5000 has two bug in the ethernet controller. first one is store invalid word in the front of receive frame buffer at the special frame length, this frame length is changed by bdma receive burst size. the second thing is mac controller is hanged after receive heavy short frame from 100 mbps network. the solution for first bug, you can see the pre-defined statement in the bdma_rx_isr() function. the invalid word in the first of receive frame buffer is same as word swapped value of previous frame descriptor ? s status and length field. so, we can check the first word with previous frame descriptor ? s status and length value. if invalid word is attached, we can move the frame buffer pointer to next 4 byte. the source code is listed in listing 3-72 . listing 3-72. KS32C5000 bug fetch code 1 (macinit.c) . . #if KS32C5000_bug_fetch u32 fstdata,fstdatasave,*fstframed ata ; #endif . . . #if KS32C5000_bug_fetch fstframedata = (u32 *)prxfdptr->framedataptr ; fstdatasave = *fstframedata ; fstdata = ( (fstdatasave<<24) & 0xff000000 ) |\ ( (fstdatasave<<8) & 0x00ff0000 ) |\ ( (fstdatasave>>24) & 0x000000ff ) |\ ( (fstdatasave>>8) & 0x0000ff00 ) ; if (gpreviousstatusfield == fstdata) pframedata = pframedata + 4 ; #endif . . . #if KS32C5000_bug_fetch gpreviousstatusfield = prxfdptr->statusandframelength ; #endif . .
diagnostic source code ks32c50100/5000a risc microcontroller 3 - 148 the solution for second bug is use a kind of watch-dog timer, in the every system has system tick timer, so we can use this timer to call ethernet watch-dog timer. in the watch-dog timer, check the receive frame descriptor pointer, and there is no change in the several times, then initialize ethernet controller receive function. the watch-dog timer for ethernet controller and initialize function is described in listing 3-73 . listing 3-73. KS32C5000 bug fetch code 2 (macinit.c) /* * function : lan_watchdog * description : lan watchdog function */ void lan_watchdog(void) { watchdogtime++ ; if ( !(watchdogtime%100) ) { if (gcrxfdptr == gpreviousfdp) { macwatchdoginit() ; } else gpreviousfdp = gcrxfdptr ; } } // initialize function for watchdog void macwatchdoginit(void) { sframedescriptor *prxfdptr ; bdmarxcon = 0x0 ; // disable bdma contoller rx operation bdmarxcon = brxrs ; // reset bdmac receiver disable_int(nbdma_rx_int) ; // disable bdma rx interrupt bdmarxlsz = maxrxframesize ; // 1520 prxfdptr = (sframedescriptor *)gcrxfdptr ; bdmarxptr = gcrxfdptr = (u32)(prxfdptr->nextframedescriptor) ; enable_int(nbdma_rx_int); bdmarxcon = gbdmarxcon ; } the sample timer interrupt service routine for call the watch-dog timer is described in listing 3-74 . this interrupt service routine can be changed by system usage.
ks32c50100/5000a risc microcontroller d iagnostic source code 3- 149 listing 3-74. tm0isr function for KS32C5000 bug fetch code 2 (timer.c) /* timer0 can be used for system real time clock */ void tm0isr(void) { clk_tick0++; iopdata = ~(1< diagnostic source code ks32c50100/5000a risc microcontroller 3 - 150 notes
ks32c50100 risc microprocessor system d esign 4- 1 4 system design overview the KS32C5000(a)/50100, snasumg's 16/32-bit risc microcontroller is cost-effective and high performance microcontroller solution for ethernet-based system. the integrated on-chip functions of KS32C5000(a)/50100 are 8k-byte unified cache/sram ethernet controller hdlc controller uart timer i2c programable i/o ports interrupt controller therefore, you can use KS32C5000(a)/50100 as amount types of system. applicable sytem with KS32C5000(a)50100 if your product need to be networked, the KS32C5000(a)/50100, snasumg's 16/32-bit risc microcontroller can be reduce your system cost. there are sample system, it can be designed with KS32C5000(a)/50100. managed hub/switch router and bridge isdn router /ta adsl router home/industry security cable modem digital camera home/industry security cable modem internet fax/internet phone network printer game machine any system with network interface
system design ks32c 50100 risc microprocessor 4- 2 meory interface design address bus generation the KS32C5000(a)/50100 address bus generation is based on the required data bus width of each memory bank, the internal system address bus is shifted out to an external address bus, addr[21:0]. this means that memory control signals such as nras[3:0], ncas[3:0], necs[3:0], nrcs[5:0], nwbe[3:0] are generated by the system manager according to a pre-configured external memory scheme (see table 4-1,and figure 4-1). table 4-1. address bus generation guidlines data bus width external address pins, addr[21:0] accessible memory size 8-bit (byte) a21-a0 (internal) 4m bytes 16-bit (half-word) a22-a1 (internal) 4m half-words 32-bit (word) a23-a2 (internal) 4m words s a [ 2 1 : 0 ] s a [ 2 2 : 1 ] d a t a b u s w i d t h c o n f i g u r a t i o n ( 8 b i t / 1 6 b i t / 3 2 b i t ) 8 _ b i t 1 6 _ b i t e x t e r n a l a d d r e s s p i n s a d d r [ 2 1 : 0 ] 2 2 _ b i t 2 2 _ b i t 2 2 _ b i t s a [ 2 3 : 2 ] 3 2 _ b i t 2 2 _ b i t i n t e r n a l e x t e r n a l s y s t e m a d d r e s s b u s : s a [ 2 5 : 0 ] figure 4-1. external address bus generation(addr[21:0])
ks32c50100 risc microprocessor system d esign 4- 3 boot rom design when system reset, a KS32C5000(a)/50100a access 0x00000000 address. and KS32C5000(a)/50100 should be configure some system variable after reset. therefore this special code (boot rom image) should be located on address 0x00000000. a boot rom can have a various width of data bus, and it is controlled by b0size[1:0] pins. table 4-2. data bus width for rom bank 0 b0size[1:0] data bus width 00 reserved 01 8-bit (byte) 10 16-bit (half-word) 11 32-bit (word) one byte boot rom design a design with one byte boot rom is shown in figure 4-2. b0size[1] b0size[0] addr[21:0] data[7:0] nrcs0 noe nwbe[0] ks32c50100 /5000a addr[18:0] data[7:0] nce noe nwe eeprom/ flash figure 4-2. one byte boot rom design make and fusing one byte rom image when make one byte rom image, you can use the binary file that maded from compile and link.
system design ks32c 50100 risc microprocessor 4- 4 half-word boot rom design with byte eeprom/flash a design with half-word boot rom with byte eeprom/flash is shown in figure 4-3. b0size[1] b0size[0] addr[21:0] data[15:0] nrcs0 noe nwbe[1:0] ks32c50100 /5000a addr[18:0] data[7:0] nce noe nwe eeprom/ flash addr[18:0] data[7:0] nce noe nwe eeprom/ flash addr[18:0] data[7:0] nwbe[0] addr[18:0] data[15:8] nwbe[1] figure 4-3. the half-word boot rom design with byte eeprom/flash make and fusing half-word rom image with byte eeprom/flash when make half-word rom image, you can split two image files, even and odd. when you use our device KS32C5000(a)/50100 as big- endian mode, then you should swap even and odd. because KS32C5000(a)/50100 has little- endian data bus structure. for example : split2 rom.bin output even file name : rom.odd out odd file name : rom.evn but, when you use our device as little- endian mode, then there is no need swap of even and odd.
ks32c50100 risc microprocessor system d esign 4- 5 half-word boot rom design with half-word eeprom/flash a design with half-word boot rom with byte eeprom/flash is shown in figure 4-4. b0size[1] b0size[0] addr[21:0] data[15:0] nrcs0 noe nwbe[1:0] ks32c50100 /5000a addr[18:0] data[15:0] nce noe nwe eeprom/ flash addr[18:0] data[7:0] nwbe[0] figure 4-4. the half-word boot rom design with half-word eeprom/flash make and fusing half-word rom image with byte eeprom/flash when make half-word rom image, you should swap even and odd rom image on rom writer. because KS32C5000(a)/50100 has little- endian data bus structure. but, when you use our device as little- endian mode, then there is no need swap of even and odd.
system design ks32c 50100 risc microprocessor 4- 6 memory banks design and control the ks32c50100 has 6 bank rom/sram banks (rom0 bank for boot rom), 4 edo/synchronous dram banks, and 4 external i/o banks,. the KS32C5000(a) has 6 bank rom/sram banks(rom0 bank for boot rom), 4 edo dram banks, and 4 external i/o banks, the system manager on KS32C5000(a)/50100 can control access time, data bus width, and base/end point, for each banks by s/w. the access time and base/end point of rom/sram banks is controlled by romcon0-5 control register on system manager. the base point of external i/o banks is controlled by refextcon control register, and access time for each external i/o banks is controlled by extcon0-1 control register. and the access time and base/end point of dram banks is controlled by dramcon0-3 control register. the care is need for attach the memory and external i/o to KS32C5000(a)/50100's, even though cpu is configured for the big- endian memory accessing. however, to connect with the external memory, KS32C5000(a)/50100 is different with the other normal big- endian microcontrollers because of its internal byte- swap mechanism. the data connection with external memory should be done as the "little endian" way. that is, the byte 0 of the external memory( that is, the most significant byte of a word)should be connected to the controller's data pin[7:0], byte 1 to data pin[15:8], byte 2 to data pin[23:16], and byte 3 to data pin[31:24]. when you use ks32c50100 with sdram, you can enable sdram mode by syscfg register bit 31. the data bus width for each rom/sram banks, external i/o banks, and dram banks is controlled by extdbwth data bus width register on system manager, except rom bank 0. the rom bank 0 is used for boot rom bank, therefore bank 0 is controlled by h/w, b0size[1:0] is used for this purpose(see table 3-2). the control of extdbwth,romcon0-5, dramcon0-4,refextcon is performed when system reset, by special command, ldmia and stmia. sample code for special register configuration is described below.
ks32c50100 risc microprocessor system d esign 4- 7 rom/sram banks design the rom/sram banks 1-5, can have a various width of data bus, and the bus width is controlled by s/w, a extdbwth special register set. a sample design for rom/sram bank 1-5 is shown in figure 4-5, figure 4-6, and figure 4-7. addr[21:0] data[8:0] nrcs[5:1] noe nwbe[0] ks32c50100 /5000a addr[21:0] data[7:0] nce noe nwe eeprom/ sram addr[18:0] data[7:0] nwbe[0] figure 4-5. one-byte eeprom/sram banks design addr[21:0] data[15:0] nrcs[5:1] noe nwbe[1:0] ks32c50100 /5000a addr[21:0] data[7:0] nce noe nwe eeprom/ sram addr[18:0] data[7:0] nwbe[0] addr[21:0] data[7:0] nce noe nwe eeprom/ sram addr[18:0] data[15:8] nwbe[1] figure 4-6. half-word eeprom/sram banks design
system design ks32c 50100 risc microprocessor 4- 8 addr[21:0] data[31:0] nrcs[5:1] noe nwbe[3:0] ks32c50100 /5000a addr[21:0] data[7:0] nce noe nwe eeprom/ sram addr[18:0] data[7:0] nwbe[0] addr[21:0] data[7:0] nce noe nwe eeprom/ sram addr[18:0] data[15:8] nwbe[1] addr[21:0] data[7:0] nce noe nwe eeprom/ sram addr[21:0] data[7:0] nce noe nwe eeprom/ sram addr[18:0] data[23:16] nwbe[2] addr[18:0] data[31:24] nwbe[3] figure 4-7. word eeprom/sram banks design
ks32c50100 risc microprocessor system d esign 4- 9 rom/sram bank 5 design with multiplexed address/data bus the KS32C5000(a)/50100 supports multiplexed address/data bus for low-cost chips which require multiplexed bus. but, rom bank5 muxed bus mode was added to KS32C5000(a)/50100 for the purpose of using special asic chip interface not commercial device. so, there are some limits using this mode, the address bus generation scheme of KS32C5000(a)/50100 is shifted address bus according to the data bus width of each memory bank. the rom bank 5 restriction is listed in below. data bus width is fixed to 32bit. so, if you want to attach 8-bit device, then you should read all 32-bit data and then process by s/w to get 8-bit real data. multiplexed address signal has same configuration with stand-alone address bus, so it can m ake exhaust accessable addressing area than real address area. that is, if you configure the data bus width of rom bank5 to word in muxed bus mode, then the muxed address will be appeared on the data bus shifted by two bits. using this mode in spite of the loss address space less then 64mbyte, you have to use trick as follows ( rom bank5 offset address + access address << n ) + byte offset. where, n is 2 in case of 32bit data bus width, 1 in case of 16bits, 0 in case of 8bits. byte offset hav e to be 0 for byte access, 1 for halfword access, 2 for word access. for example, you want to access half-word 0x123 address, translated address is as follows: 0x123 << 2 + 3 = 0x48f you can use the mclko clock output as a target device.
system design ks32c 50100 risc microprocessor 4- 10 edo dram banks design for KS32C5000(a)/50100 the dram banks 0-4, can have a various width of data bus, and the bus width is controlled by s/w, a extdbwth special register set. a sample design for dram bank 0-3 is shown in figure 4-8, figure 4-9, and figure 4-10. addr[21:0] data[31:0] nras ncas[3:0] ndwe ks32c50100 /5000a addr[11:0] data[7:0] nras ncas nw addr[11:0] data[7:0] ncas[0] edo dram figure 4-8. 1-byte edo/normal dram banks design
ks32c50100 risc microprocessor system d esign 4- 11 addr[21:0] data[31:0] nras ncas[3:0] ndwe ks32c50100 /5000a addr[11:0] data[7:0] nras ncas nw addr[11:0] data[7:0] ncas[0] addr[11:0] data[7:0] nras ncas nw addr[11:0] data[15:8] ncas[1] edo dram edo dram figure 4-9. half-word edo/normal dram banks design
system design ks32c 50100 risc microprocessor 4- 12 addr[21:0] data[31:0] nras ncas[3:0] ndwe ks32c50100 /5000a addr[11:0] data[7:0] nras ncas nw addr[11:0] data[7:0] ncas[0] addr[11:0] data[7:0] nras ncas nw addr[11:0] data[15:8] ncas[1] addr[11:0] data[7:0] nras ncas nw addr[11:0] data[7:0] nras ncas nw edo dram addr[11:0] data[23:16] ncas[2] addr[11:0] data[31:24] ncas[3] edo dram edo dram edo dram figure 4-10. word edo/normal dram banks design
ks32c50100 risc microprocessor system d esign 4- 13 synchronous dram banks design for ks32c50100 the ks32c50100 synchronous dram interface features are as follows : maximum column address of sdram: 11bit cas latency: 2 cycle burst lengyh support: only 1 burst mode(single mode) support burst type: sequential support auto refresh ks32c50100 can support below samsung ? s sdram configuration for each bank. 16m sdram km44s4020c: 2m x 4bit with 2 banks km48s2020c: 1m x 8bit with 2 banks km416s1020c: 512k x 16bit x 2 banks 64m 2 banks sdram km44s16020b: 8m x 4bit with 2 banks km48s8020b: 4m x 8bit with 2 banks km416s4020b: 2m x 16bit x 2 banks 64m 4 banks sdram km44s16030b/c: 4m x 4bit with 4 banks km48s8030b/c: 2m x 8bit with 4 banks km416s4030b/c: 1m x 16bit x 4 banks 2mx32 4 banks sdram km432s2030b: 512k x 32bit with 4 banks when you desgn with sdram, you should enable mclko pin for sdram sync. clock. and address 10 is used for bank address (ba) select address for sdram. the required sdram interface pin is cke, sdclk, nsdcs[3:0], nsdcas, nsdras, dqm[3:0], addr[10]/ap. the sample design with sdram is shown in figure 4-11, and figure 4-12. when you design with 5 v device with 3.3 v sdram, then you need to protect the 3.3 v sdram from 5 v device. that is, data bus should be has 10 ohm damping resister from 5 v device.
system design ks32c 50100 risc microprocessor 4- 14 addr[10:0] addr[11]/ba data[31:0] mclko/sdclk nras[3:0]/nsdcs[3:0] ncas0/nsdras ncas1/nsdcas ndwe nwbe[3:0]/dqm[3:0] ks32c50100 addr[10:0] data[7:0] dqm[0] sync dram addr[10:0] ba0 data[7:0] clk ncs nras ncas nwe dqm sync dram addr[10:0] ba0 data[7:0] clk ncs nras ncas nwe dqm sync dram addr[10:0] ba0 data[7:0] clk ncs nras ncas nwe dqm sync dram addr[10:0] ba0 data[7:0] clk ncs nras ncas nwe dqm addr[10:0] data[15:8] dqm[1] addr[10:0] data[23:16] dqm[2] addr[10:0] data[31:24] dqm[3] 10ohm 10ohm 10ohm 10ohm figure 4-11. sdram design with 1-byte components
ks32c50100 risc microprocessor system d esign 4- 15 addr[10:0] addr[11]/ba data[31:0] mclko/sdclk nras[3:0]/nsdcs[3:0] ncas0/nsdras ncas1/nsdcas ndwe nwbe[3:0]/dqm[3:0] ks32c50100 addr[10:0] data[15:0] dqm[1:0] sync dram addr[10:0] ba0 data[15:0] clk ncs nras ncas nwe ldqm/udqm sync dram addr[10:0] ba0 data[31:16] clk ncs nras ncas nwe ldqm/udqm addr[10:0] data[31:0] dqm[3:2] 10ohm 10ohm figure 4-12. sdram design with half-word components
system design ks32c 50100 risc microprocessor 4- 16 external i/o banks design the external i/o banks 0-3, can have a various width of data bus, and the bus width is controlled by s/w, a extdbwth special register set. a design with external i/o banks 0-3 to memory-like device is similar to rom/sram banks 1-5. for a very slow device, the KS32C5000(a)/50100 provide external wait request signal ( newait). to use this request signal, you set the tcos and tcoh should not be zero. and newait signal should be assert, as soon as possible, the necs chip select signal is asserted. for detail timing for use of newait, you can see KS32C5000(a)/50100 user's manual, system manager block description. the sample design timing diagram with necs and newait is deficted in below figure 4-13. mclk la[21:0] valid address necs noe/nwbe newait tcos tcoh nready (from external slow device) - newait signal is maded from necs, mclk, nready signal - tcos, tcoh should be over than one cycle figure 4-13. external slow device design with newait signal
ks32c50100 risc microprocessor system d esign 4- 17 1. sample design with external i/o banks: general uart chipset interface in this design, we use external i/o bank 0, and one byte data bus width. the external i/o access cycle should be configured as proper value, by software. KS32C5000(a) interface vdd_5 vdd_5 vdd_5 euarttx addr0 xdata1 noe nxeuartcd nxeuartrts neuartcts neuartrts addr1 xdata2 xdata5 addr[2..0] neuartdsr euartint xdata[7..0] nxeuartcts neuartcd nxeuartdsr necs0 euartrx xdata6 addr2 xdata3 xdata7 nwbe[3..0] xeuarttxd nwbe0 reset xdata0 xdata4 nxeuartdtr xeuartrxd neuartdtr c? 0.1uf + c? 0.1uf + u? max232 c1+ 1 c1- 3 c2+ 4 c2- 5 t1o 14 r1i 13 t2o 7 r2i 8 vcc 16 v+ 2 v- 6 gnd 15 t1i 11 r1o 12 t2i 10 r2o 9 c? 0.1uf + y? 1.8432mhz u? max232 c1+ 1 c1- 3 c2+ 4 c2- 5 t1o 14 r1i 13 t2o 7 r2i 8 vcc 16 v+ 2 v- 6 gnd 15 t1i 11 r1o 12 t2i 10 r2o 9 r? 1m c? 0.1uf + c? 27pf c? 0.1uf + c? 0.1uf + c? 27pf u? st16c550 16550 ( 44pin plcc ) d0 2 d1 3 d2 4 d3 5 d4 6 d5 7 d6 8 d7 9 a0 31 a1 30 a2 29 reset 39 niow 20 nior 24 cs0 14 cs1 15 ncs2 16 int 33 tx 13 ndtr 37 nrts 36 rx 11 ndsr 41 ncts 40 ncd 42 nri 43 rclk 10 baudout 17 nop1 38 nop2 35 ior 25 iow 21 nddis 26 nas 28 ntxrdy 27 nrxrdy 32 xtal1 18 xtal2 19 nc1 1 nc12 12 nc23 23 nc34 34 vcc44 44 gnd22 22 c? 0.1uf + c? 0.1uf + addr[21..0] reset euartint necs0 nwbe[3..0] noe xdata[31..0] figure 4-14. external uart chipset interface design
system design ks32c 50100 risc microprocessor 4- 18 2. sample design with external i/o banks: super-i/o in this design, we use external i/o bank 0, and one byte data bus width. the external i/o access cycle should be configured as proper value, by software. and you can refer datasheet of super-i/o device for more detail operation. off: 250h ( bios address default ) cr address setting half on : 3f0h to external interrupt this port should be set to proper use vcc vcc vcc vcc vcc vcc vcc addr6 xdata7 addr2 addr5 addr1 xdata2 xdata0 necs0 addr10 addr0 xdata5 addr4 xdata6 xdata4 addr9 addr3 reset hefras addr7 xdata3 xdata1 addr8 r105 4.7k l7 l3216 r110 4.7k u? w83877tf cs# 2 a0 51 a1 52 a2 53 a3 54 a4 55 a5 57 a6 58 a7 59 a8 60 a9 61 a10 75 d0 66 d1 67 d2 68 d3 69 d4 70 d5 71 d6 72 d7 73 mr 6 aen 62 iochrdy/pled 5 ior# 63 iow# 64 t/c 97 irqc/irq3 44 irqd/irq4 37 irqf/irq6 99 irqe/irq7 23 drqa/drq1 39 dacka#/dack1# 41 drqb/drq2 100 dackb#/dack2# 98 drqc/drq3 4 dackc#/dack3# 18 clkin 7 smi# 8 irqa/gio1 96 irqb/gio0 92 irqg/pciclk 1 irqh/serirq 91 irrx2 94 irtx2 95 irqin 93 sci# 3 rwc# 87 index# 81 moa# 79 dsb# 84 dsa# 83 mob# 80 dir# 89 step# 82 wd# 86 we# 85 trak0# 78 wp# 77 rdata# 74 head# 88 dskchg# 76 ctsa# 34 dsra# 33 dcda# 32 ria# 31 sina 30 souta/penfdc 38 dtra#/hefras 35 rtsa#/ppnpcvs 36 ctsb# 47 dsrb# 48 dcdb# 49 rib# 50 sinb 42 soutb/psmisci 43 dtrb#/penpll 46 rtsb#/pgoiqsel 45 err# 29 ack# 26 busy 24 pe 27 slct 28 slin# 22 init# 21 afd# 20 stb# 19 pd3 12 pd4 13 pd5 14 pd6 16 vcc 15 vcc 56 vss 25 vss 40 vss 65 vss 90 pd0 9 pd1 10 pd2 11 pd7 17 r112 4.7k c88 0.1uf + r104 4.7k r114 4.7k r106 4.7k y2 14.318mhz nc 1 gnd 2 vcc 4 out1 3 r111 4.7k r109 4.7k r113 4.7k r107 4.7k r103 4.7k r108 4.7k r106 4.7k r115 4.7k nwbe0 ria dcda addr[21:0] rtsa ctsa xdata[31:0] dsra souta noe necs0 dtra sina irq_uart reset figure 4-15. super-i/o interface design
ks32c50100 risc microprocessor system d esign 4- 19 3. sample design with external i/o banks: isa bus interface design the isa bus has 16 bit data bus width and i/o, memory operation with 8mhz master clock, so we need some kinds of epld or cpld for design isa bus interface. the access cycle and data bus width should be setted to proper value for generate isa interface signal. bclk nintr a[23:0] sd[15:0] nmemcs16 niocs16 nmemr nior nmemw niow bale sbhe niochrdy isa bus interface KS32C5000(a)/ ks32c50100 mclko eintr la[21:0] ld[15:0] necs noe nwbe newait devided by 4 for KS32C5000(a) devided by 6 for ks32c50100 generate nmemcs16 or niocs16 signal from external i/o chip select signal generate nmemr or nior signal from noe signal, and generate nmemw or niow signale from nwbe signal generate newait signal for KS32C5000(a)/ks32c50100 with niochrdy and mclko signal epld or cpld figure 4-16. isa bus interface design
system design ks32c 50100 risc microprocessor 4- 20 mclko la[21:0] valid address necs noe/nwbe newait tcos tcoh niochrdy - newait signal is maded from necs, mclk, niochrdy signal - tcos, tcoh should be over than one cycle bclk nmemcs nmemr/nmemw figure 4-17. isa bus interface timing diagram
ks32c50100 risc microprocessor system d esign 4- 21 4. sample design with external i/o banks and rom/sram bank: pci bus interface design the pci bus is 32bit synchronous bus, this block diagram is KS32C5000(a)/ks32c50100 with pci host bridge controller, the pci bus general features are 32bit address/data bus high bandwidth (up to 132mb/sec@33mhz) full multi-master capability auto-configuration of devices the pci host bridge features are generate configuration cycle genera te interrupt acknowledge cycle arbitration function for all pci master when we access pci bus as pci host bridge, we have three memory space, memory space i/o space pci configuration space this three memory space make some consideration, when we design pci host bridge interface with samsung ? s KS32C5000(a)/ks32c50100, we should be careful, because KS32C5000(a)/ks32c50100 has total 64mb address range. this application block diagram for pci host bridge interface is designed with plx9080. the direct master cycle is more easy to implement than direct slave cycle. but you should be careful when you generate address for pci bus. the sample block diagram is deficted in figure 4-18.
system design ks32c 50100 risc microprocessor 4- 22 bclk linto pla[23:2] ld[31:0] plx9080 (pci host bridge) KS32C5000(a)/ ks32c50100 mclko eintr0 la[21:0] ld[31:0] for KS32C5000(a), mclko is directly used, but when use ks32c50100 is used you need more consideration epld or cpld eintr1 lserr linti p0 p1 p2 useri usero nwbe[3:0] noe pla[1:0] necs[1:0] pla[31:24] - pla[31:24] can be generated from necs[1:0] and some la[21:0] - pla[23:2] can be generated from la[21:0] - pla[1:0] can be generated from nwbe[1:0] nads nblast nreadyo nwaiti newait generate newait signal from nready signal plx9080 mode: c-mode, 32bit non-multiplexed bus mode admode: 1'b => use s[2:0] s[2:0]: 101'b => pci memory area s[2:0]: 110'b => configuration register area bigend#: 1'b => use little-endian mode. KS32C5000(a)/ks32c50100 operate as big, but data bus architecture is little-endian format figure 4-18. pci bus direct master block diagram the detail timing diagram for direct master single write/read operation is described in figure 4-19, figure 4-20.
ks32c50100 risc microprocessor system d esign 4- 23 mclko necs noe/nwbe newait tcos tcoh - newait signal is maded from necs, mclk, nreadyo signal - tcos, tcoh should be over than one cycle nblast nads nreadyo figure 4-19. pci bus direct master write timing
system design ks32c 50100 risc microprocessor 4- 24 mclko necs noe/nwbe newait tcos tcoh - newait signal is maded from necs, mclk, nreadyo signal - tcos, tcoh should be over than one cycle nblast nads nreadyo newaiti data valid read data figure 4-20. pci bus direct master read timing
ks32c50100 risc microprocessor system d esign 4- 25 ethernet interface interface overview the KS32C5000(a)/ks32c50100 ethernet media access controller operates at ether 100 mbps or 10 mbps in halh-duplex or full-duplex mode. and the ethernet controller on the KS32C5000(a)/ks32c50100 supports both 10m/100m media independent interface (mii) and old style 10m 7-wire interface. the KS32C5000(a)/ks32c50100 ethernet interface require physical line interface to connect a network. phy, a physical line interface chip, is used for interface in a 10m or 100m network. phy usually supports mediag independent interface(mii) or serial interface. 10m/100mbps mii interface mii (media independent interface) has control, data, and clock signal for the communication between ethernet mediag access controller (mac) and phy. and has a serial communication port for manage each phy, called for station management. the standard mii interface between mac and phy is shown in figure 4-21. tx_clk/txclk_10m tx_en/txen_10m txd[3:0]/txd_10m tx_err rx_err rx_clk/rxclk_10m rxd[3:0]/rxd_10m KS32C5000(a)/ks32c50100 mac(media access controller) mii interface rx_dv/link_10m crs/crs_10m col/col_10m station management mdc mdio txclk txen txd[3:0] txer rxer rxclk rxd[3:0] rxdv crs col mdc mdio 10/100m phy (physical line interface) transmit clock transmit enable transmit data[3:0] transmit error receive clock receive data valid receive data[3:0] receive error carrier sense collision detected management data clock management data input/output figure 4-21. mii connection with phy
system design ks32c 50100 risc microprocessor 4- 26 1. sample design with 10/100mbps mii interface phy: ics1890 you can refer ics1890 datasheet for the detail specification. the configuration of ics1890 is decided by your system usage. vcc vcc vcc_r vcc_t vcc vcc vcc gnd_ r gnd_ t 25 mhz phy clock osc * setted to phy id #1 - p3td: phy id3/transmit data led - p1cl: phy id1/collision detected - p2li: phy id2/link integrity led * led status - p0ac: phy id0/activity led - p4rd: phy id4/receive data led configured as your purpose ref_in nod/rep 10/100sel nitcls mii/si hw/sw dpxsel 10/lp ansel tptri rxtri p0ac p1cl p2li p3td p4rd rxd3 rxd2 rxd1 rxd0 txd0 txd1 txd2 txd3 p3td p4rd p2li p0ac p1cl r39 1.5k 1 2 r64 2.4k 1 2 r65 6.81k 1 2 r53 33 1 2 r52 33 1 2 r49 33 1 2 r45 33 1 2 r44 33 1 2 r46 33 1 2 r51 33 1 2 r61 33 1 2 r60 33 1 2 r58 33 1 2 r56 33 1 2 r55 33 1 2 r57 33 1 2 r59 33 1 2 r63 33 1 2 r62 33 1 2 c3 0.1uf + 1 2 c4 10uf + 1 2 c11 0.1uf + 1 2 c12 10uf + 1 2 r33 110 1 2 r37 49.9 1 2 r36 49.9 1 2 c7 0.1uf + 1 2 r32 50 1 2 r34 50 1 2 r35 50 1 2 c5 0.01uf + 1 2 r48 50 1 2 r42 50 1 2 r41 50 1 2 c10 0.01uf + 1 2 c8 0.1uf + 1 2 u5 ics1890 phy nod/rep 1 10/100sel 2 10tcsr 3 100tcsr 4 tp_tx+ 5 tp_tx- 6 vss_7 7 vdd_8 8 tptri 9 tp_rx+ 10 tp_rx- 11 nc_12 12 itcls 13 nc_14 14 nc_15 15 vdd_16 16 vss_17 17 vdd_18 18 mii/si 19 reg 20 lsta 21 reset 22 hw/sw 23 dpxsel 24 vdd_25 25 nc_26 26 lock 27 10/lp 28 vss_29 29 mdio 30 mdc 31 rxd3 32 rxd2 33 rxd1 34 rxd0 35 rxdv 36 rxclk 37 rxer 38 rxtri 39 vss_40 40 vdd_41 41 txer 42 txclk 43 txen 44 txd0 45 txd1 46 txd2 47 txd3 48 col 49 crs 50 vss_51 51 ref_out 52 ref_in 53 vdd_54 54 vss_55 55 vdd_56 56 vdd_57 57 p0ac 58 p1cl 59 p2li 60 p3td 61 p4rd 62 vss_63 63 ansel 64 r47 75 1 2 c9 0.1uf + 1 2 r31 75 1 2 u6 pe68517 td+ 1 td- 2 ct_3 3 cmt_6 6 tx- 7 tx+ 8 rd- 16 rd+ 15 ct_14 14 cmt_11 11 rx+ 10 rx- 9 nc_4 4 nc_13 13 j9 rj45 tx+ 1 tx- 2 rx+ 3 p4 4 p5 5 rx- 6 p7 7 p8 8 r30 22 1 2 l3 l3216 1 2 c6 0.1uf + 1 2 u4 osc nc 1 gnd1 4 gnd2 7 out2 8 out1 11 vcc 14 r40 1k 1 2 d14 led 1 2 r54 1k 1 2 d11 led 1 2 r38 1k 1 2 d13 led 1 2 r50 1k 1 2 r43 1k 1 2 d15 led 1 2 d12 led 1 2 nreset mdio mdc rxd[3:0] rxdv rxclk rxer txclk col crs txd[3:0] txen txer figure 4-22. sample design with ics1890 phy
ks32c50100 risc microprocessor system d esign 4- 27 2. sample design with 10/100mbps mii interface phy : lxt970 you can refer lxt970 datasheet for the detail specification. vddd vddd vddd vddd vddd r13 49.9 d2 led c26 0.1uf r17 100 r15 22k 1% r18 1k r8 680 r59 1k c30 0.1uf r19 2k c25 0.1uf r9 680 j1 xfatm2-combo- cmt 1 ct_t 2 tx+ 3 tx- 4 nc 5 ct_r 6 rx+ 7 rx- 8 d1 led d5 led c20 0.1uf d27 led d3 led c23 10uf + c28 10uf + l4 f.b. u4 levelone col 64 txclk 57 txd3 62 txd2 61 txd1 60 txd0 59 txen 58 txer 56 crs 1 rxclk 54 rxd3 47 rxd2 48 rxd1 49 rxd0 50 rxdv 51 rxer 55 mdc 45 mdio 44 nreset 16 leds 38 ledc 39 ledl 40 ledt 41 ledr 42 xi 12 x0 11 pwrdwn 34 vddd 9 vddo 53 mdint 2 gndd 43 gndo 52 test 10 mf0 8 mf1 7 mf2 6 mf3 5 mf4 4 fibp 27 fibn 28 fibop 17 fibon 18 rbias 25 tref 20 tpop 21 tpon 23 trip 29 trin 30 vcct 19 gndt 22 vcca 24 gnda 26 vccr 37 gndr 31 r14 49.9 r11 680 c22 0.001uf/2kv l2 f.b. r7 680 l3 f.b. d4 led r20 10k r10 680 l1 f.b. c24 10uf + c27 0.1uf c21 0.1uf c31 0.1uf u5 osc(25mhz nc 1 vdd 8 gnd 4 out 5 r21 22 l5 f.b. rxd[0..3] rxdv mdio col nreset rxclk txclk txer crs rxer txd[0..3 mdc txen figure 4-23. sample design with lxt970 phy
system design ks32c 50100 risc microprocessor 4- 28 3. sample design with 10/100mbps mii interface to ric : lxt980 you can refer lxt980 datasheet for the detail specification. gnd_v vcc_t vdd_5 gnd_r vdd_5 gnd_t gnd_t vdd_5 vdd_5 gnd_t vdd_5 vdd_5 vcc_v gnd_r gnd_t gnd_r gnd_a vcc_r gnd_t vdd_5 vdd_5 vdd_5 gnd_r gnd_r gnd_t vdd_5 vdd_5 vdd_5 25mhz : phy clock down : local manager present(will be used) redundant power not used chip id is 0 port5 is phy mode arbitration chain based not used up : local manager not present serial clock receive nir10cfs nir100cfs nir10col rcvled1 faultled mmstrout rcvled4 spdled1 gndt arbout ledsel1 linkled1 rxd3 ir100data4 ir10clk arbout act100led act10led vccv rxd2 mmstrin ir100clk ir100data2 rcvled3 ledsel0 gndr gndv ir100data1 nir100den ledsel1 txd2 holdcol linkled5 gndt nir100cfsbp nir100sngl rbias txd1 ir10data nir10ena nir10cfsbp vcct txd0 rxd0 nir100col nir10den arbin mmstrout spdled5 spdled4 linkled4 gnda ir100data0 nir10colbp ledsel0 linkled3 txd3 arbin nir100dv spdled3 ir100data[4..0] ir100iso ir10iso mgrled col100led holdcol rcvled2 rcvled5 spdled2 vccr rxd1 ir100data3 mmstrin col10led linkled2 act100led spdled4 linkled4 rcvled3 rcvled2 spdled1 rcvled4 faultled linkled1 col100led linkled3 act10led spdled2 spdled3 col10led linkled2 rcvled1 nir10cfs txclk rxdv port_spd0 nir10den nir10cfsbp port_spd1 ir10iso arbin crs txdb ir100iso nir100dv nir100cfs ir100data[4..0] nrst txcb nir100col mmstrout col nir10col nir100sngl arbout holdcol nir10ena ir100clk txer nir10colbp ir100clk rxer rxclk txd[0..3] mmstrin rxd[0..3] nir100cfsbp ir10data nir100den txen rxdb r? 4.7k r? 4.7k r? 22 r? 1k r? 4.7k r? 200 r? 200 r? 200 r? 4.7k r? 680 r? 200 r? 4.7k r? 4.7k r? 182 r? 200 r? 200 u? osc 25mhz nc 1 vdd 8 gnd 4 out 5 r? 200 r? 200 r? 200 r? 200 r? 200 c? 0.1uf r? 200 r? 4.7k r? 4.7k r? 1k r? 4.7k r? 4.7k l? f.b. r? 4.7k r? 200 r? 330 r? 200 r? 200 r? 200 u? lxt980 lxt980 port1_spd0 189 port1_spd1 188 port2_spd0 187 port2_spd1 186 port3_spd0 185 port3_spd1 184 port4_spd0 183 port4_spd1 182 port5_spd 100 port5_sel 99 config0 197 config1 196 config2 195 config3 194 config4 193 config5 192 config6 191 config7 190 mii_rxd2 32 mii_rxd3 33 mii_rxdv 26 mii_rxclk 25 mii_rxer 24 mii_rxd0 29 mii_rxd1 30 mii_txer 22 mii_txclk 21 mii_txen 20 mii_txd0 19 mii_txd1 18 mii_txd2 17 mii_txd3 16 mii_col 14 mii_crs 13 mmstrin 199 mmstrout 63 nir100cfs 36 nir100cfsbp 37 nir100sngl 38 nir100col 40 nir100den 41 nir100dv 42 ir100dat0 43 ir100dat1 44 ir100dat2 45 ir100dat3 46 ir100dat4 49 ir100clk 52 ir100iso 56 ir10dat 9 ir10clk 10 nir10den 6 nir10ena 8 nir10col 3 nir10colbp 4 nir10cfs 1 nir10cfsbp 5 macactive 79 ir10iso 55 holdcol 80 tpop1 149 tpon1 151 tpop2 136 tpon2 138 tpop3 121 tpon3 123 tpop4 108 tpon4 110 tpip1 146 tpin1 147 tpip2 133 tpin2 134 tpip3 118 tpin3 119 tpip4 105 tpin4 106 fibop1 153 fibon1 154 fibop2 140 fibon2 141 fibop3 125 fibon3 126 fibop4 112 fibon4 113 fibip1 157 fibin1 156 fibip2 144 fibin2 143 fibip3 129 fibin3 128 fibip4 116 fibin4 115 sigdet1 155 sigdet2 142 sigdet3 127 sigdet4 114 reconfig 58 ser_match 62 srx 59 stx 60 serclk 61 arbin 198 arbout 64 arbselect 65 nmgr_pres 66 ledsel0 208 ledsel1 207 port1_led1 181 port2_led1 177 port3_led1 173 port4_led1 166 port5_led1 162 port1_led2 180 port2_led2 176 port3_led2 172 port4_led2 165 port5_led2 161 port1_led3 179 port2_led3 175 port3_led3 171 port4_led3 164 port5_led3 160 col10_led 85 col100_led 86 mgr_led 87 act10_led 90 act100_led 91 fauld_led 92 rps_led 98 nreset 53 clk25 54 chipid0 71 chipid1 72 chipid2 73 nirq 81 vcc12 12 vccr107 107 vccr120 120 vccr135 135 vccr148 148 vcct111 111 vcct124 124 vcct139 139 vcct152 152 vccv94 94 vccv169 169 vcc28 28 vcc35 35 vcc51 51 vcc57 57 vcc76 76 vcc84 84 vcc89 89 vcc96 96 vcc170 170 vcc201 201 vcc203 203 vcc206 206 gndt109 109 gndt122 122 gndt137 137 gndt150 150 gndr104 104 gndr117 117 gndr132 132 gndr145 145 gnda27 27 gnda130 130 rbias 131 gndv95 95 gndv168 168 gnd2 2 gnd11 11 gnd34 34 gnd50 50 gnd74 74 gnd75 75 gnd82 82 gnd83 83 gnd88 88 gnd93 93 gnd158 158 gnd159 159 gnd163 163 gnd167 167 gnd174 174 gnd178 178 gnd200 200 gnd202 202 rps_pres 78 nrps_fault 77 prom_cl k 67 prom_c s 68 prom_dtou t 69 prom_dtin 70 nc7 7 nc15 15 nc23 23 nc31 31 nc39 39 nc47 47 nc48 48 nc97 97 nc101 101 nc102 102 nc103 103 r? 330 r? 330 d? led r? 330 r? 330 r? 330 d? led d? led r? 330 d? led r? 330 r? 330 d? led r? 330 r? 330 d? led d? led d? led r? 330 d? led d? led d? led r? 330 d? led d? led d? led d? led d? led d? led 98 76 figure 4-24. sample design with lxt980 4-port ric
ks32c50100 risc microprocessor system d esign 4- 29 10m 7-wire interface 7-wire interface only for 10m ethernet has control, data, and clock signal for the communication between ethernet mediag access controller (mac) and phy. the standard 7-wire interface between mac and phy is shown in figure 4-25. tx_clk/txclk_10m tx_en/txen_10m txd[0]/txd_10m rx_err rx_clk/rxclk_10m rxd[0]/rxd_10m KS32C5000(a)/ks32c50100 mac(media access controller) 7-wire interface rx_dv/link_10m crs/crs_10m col/col_10m txclk txen txd rxclk rxd rxdv crs col 10m phy (physical line interface) transmit clock transmit enable transmit data receive clock receive data valid receive data carrier sense collision detected figure 4-25. 7-wire interface with 10m phy
system design ks32c 50100 risc microprocessor 4- 30 1. sample design with 10mbps 7-wire interface: lxt901a/970a you can refer lxt901/lxt970a datasheet for the detail specification. magneytic rj45 twist-pair interface aui port magneytic aui interface vcc vcc vcc vcc ledl ledt ledr ledc r38 4.7k r49 4.7k r43 12.4kr/1% r44 510 r37 4.7k r47 4.7k r42 510 c31 0.1uf r46 4.7k r45 4.7k r36 4.7k r39 4.7k r40 510 r48 4.7k r41 510 l1 l3216 r51 4.7k u5 lxt901a lxt 901a/907a vcc1 10 cip 11 cin 12 nth 13 md0 14 md1 15 li 19 jab 21 test 22 tclk 23 txd 24 ten 25 clko 26 clki 27 col 28 autosel 29 ledr 34 ledt/pdn* 35 ledl 36 ledc/fde* 37 lbk 38 gnd1 39 rbias 42 gnda 40 rxd 45 cd 46 rclk 47 vcca 9 plr 52 tpopb 53 tpopa 54 gnd2 55 vcc2 56 tpona 57 tponb 58 utp/stp* 59 tpip 61 tpin 62 paui 3 dip 4 din 5 dop 7 don 8 nc 1 nc 2 nc 6 nc 16 nc 17 nc 18 nc 20 nc 30 nc 31 nc 32 nc 33 nc 43 nc 41 nc 44 nc 48 nc 49 nc 50 nc 51 nc 60 nc 63 nc 64 c? 27pf y? 20mhz c? 27pf r11 330 r10 330 d4 led d3 led d5 led r9 330 r8 330 d2 led r? 50 r? 50 c? 0.1uf r? 24.9/1% r? 24.9/1% r? 78 r? 78 r? 78 txd[0](txd_10m) txd[1](loop_10m) tx_en(txen_10m) tx_clk(txclk_10m) rx_clk(rxclk_10m) rxd[0](rxd_10m) crs(crs_10m) col(col_10m) figure 4-26. sample design with lxt901a/970a (auto port select support)
ks32c50100 risc microprocessor system d esign 4- 31 system design with debugger support embeddedice macrocell and embeddedice interface the KS32C5000(a)/ks32c50100 has an embeddedice macrocell that provides debug support fro arm cores. the embeddedice macrocell is programmed in serial using the tap(test access port) controller on the KS32C5000(a)/ks32c50100. the embeddedice interface is a jtag protocol conversion unit. it translates a debug protocol message generated by the debugger into a jtag signal which is sent to the built-in serial and parallel ports. jtag port for embeddedice interface when you build a system with the KS32C5000(a)/ks32c50100 embeddedice interface. you should design a jtag port for embeddedice interface. usually, the interface connector is a 14-way box header, and this plug is connected to the embeddedice interface module using 14-way idc cable. the jtag port signals, ntrst,tdi,tms, are internally pulled high, while tdo is internally pulled low which makes pull-up, and pull-down resisters unnecessary. the pin configuration and a sample design are described in figure 4-27, 4-28, respectively. 2 1 4 3 6 5 8 7 9 10 11 12 14 13 pin name function 1,13 spu connected to vdd through 33 or 0 ohm resister* 3 ntrst test reset, active low 5 tdi test data in 7 tms test mode select 9 tck test clock 11 tdo test data out 12 nicerst connected to vdd through 10k ohm resister 2,4,6,8,10,14 vss system ground * 33 ohm for embeddedice, 0 ohm for multi-ice figure 4-27. embeddedice interface jtag connector
system design ks32c 50100 risc microprocessor 4- 32 33 ohm / 0 ohm 2 1 4 3 6 5 8 7 9 10 11 12 14 13 KS32C5000(a)/ ks32c50100 nreset ntrst tdi tms tck tdo nc gnd vcc vcc gnd nreset (from reset logic) 10k ohm 5k ohm 10uf jumper jumper in : normal operation jumper out : debug mode figure 4-28. embeddedice interface design example
ks32c50100 risc microprocessor system d esign 4- 33 check list for system design with KS32C5000(a)/ks32c50100 when you design a system with the KS32C5000(a)/ks32c50100, you should check a number of items to build a good system. the check list is described below. the b0size[1:0] signals are correctly configured to your boot rom size. an newait signal has a pull-up resister. an extmreq signal has a pull-down resister. address bus interface to a memory system, that has a different internal and external address bus. there is a jtag port for debugging. the reset logic for debugging interface. specially, ntrst and nreset pin. pll logic for ks32c50100
system design ks32c 50100 risc microprocessor 4- 34 notes
ks32c50100/5000a risc microcontroller o ther technical issues 5- 1 5 other technical iss ues how to run rom code on dram? when we access rom or flash rom, the access cycle is slow, so it makes system performance reduction. specially, arm core use base of boot rom area, from 0x00 to 0x1c, as a exception vector area, so cpu should access the base address of boot rom area when interrupt is issued. in our diagnostic code also use the base address of boot rom, as an exception vector area. that is, when interrupt is occurred, cpu branch to exception area to fetch exception handler area. now, we ? ll introduce the method to dram as a boot area. when use dram as boot area, the access cycle is reduced than rom device access cycle, so the system performance is grows up. the procedure to make dram as boot area at the first time, rom bank 0 used as boot rom area. after boot, the all code on rom bank 0 is copied to dram. the first all memory map is following the snds100 diagnostic code, rom bank 0 base address is 0x00000000, and dram bank 0 base address is 0x1000000. after copy the code to dram, change the memory map to dram bank 0 as address 0x00000000, and rom bank 0 as 0x1000000. the detail procedure to make dram as boot area is shown in figure 5-1. after doing this procedure, all boot code is running on the dram, even though exception vector table. the memory map difference between first boot and after change memory map is shown in figure 5-2.
other technical issues ks32c50100/5000a risc microcontroller 5- 2 start-up (power on/reset) define entry point sdram ? normal/edo dram & system memory map is configured edo dram r/w test from dram_base r/w ok ? copy rom image to normal/edo dram re-configure memory map rom #0 : 0x1000000 dram #0 : 0x0000000 sync dram & system memory map is configured copy rom image to sync dram re-configure memory map rom #0 : 0x1000000 dram #0 : 0x0000000 initialize stack pointer initialize the r/w memory area required by c-code change the processor to user mode call c_entry no yes yes no figure 5-1. the boot procedure when dram as boot area
ks32c50100/5000a risc microcontroller o ther technical issues 5- 3 rom bank 0 (boot rom) 0x0000000 0x0200000 rom bank 1~5 not used dram bank 0 0x1000000 0x1400000 dram bank 1~3 not used dram bank 0 (boot code) 0x0000000 0x0400000 dram bank 1~3 not used rom bank 0 ( first boot rom) 0x1000000 0x1200000 rom bank 1~3 not used before change memory map after change memory map exception table 0x0000000 0x0000020 code area data r/w area & stack area user area 0x03ffffff figure 5-2. the system memory map when dram as boot area
other technical issues ks32c50100/5000a risc microcontroller 5- 4 the assembler source code to make dram as boot area the assembler start-up source code to make dram as boot area is some different from original snds100 start-up code. some code is omitted from original snds100 start-up code, and some code is attached. the source code for make dram as boot area is described in below listing 5-1, also in the source code, you can found the different point between original one, and the make dram as boot area. listing 5-1. start-up code to make dram as boot area (init.s) get memory.a get snds.a import |image$$ro$$base| ; base of rom code (=start of rom data) import |image$$ro$$limit| ; end of rom code (=start of rom data) import |image$$rw$$base| ; base of ram t o initialise import |image$$rw$$limit| ; limit of ram to initialise import |image$$zi$$base| ; base and limit of area import |image$$zi$$limit| ; to zero initialise area init, code, readonly ; --- define entry point export __main ; defined to ensure that c runtime system __main ; is not linked in entry ; --- setup interrupt / exception vectors if :def: rom_at_address_zero ; if the rom is at address 0 this is just a sequence of branches b reset_handler b systemundefinedhandler b systemswihandler b systemprefetchhandler b systemaborthandler nop ; reserved vector b systemirqhandler b systemfiqhandler else ; otherwise we copy a sequence of ldr pc instructions over the vectors ; (note: we copy ldr pc instructions because branch instructions ; could not simply be copied, the offset in the branch instruction ; would have to be modified so that it branched into rom. also, a ; branch instructions might not reach if the rom is at an address ; > 32m). mov r8, #0 adr r9, vector_init_block ldmia r9!, {r0-r7} stmia r8!, {r0-r7} ldmia r9!, {r0-r7} stmia r8!, {r0-r7} ; now fall into the ldr pc, reset_addr instruction which will continue ; execution at 'reset_handler'
ks32c50100/5000a risc microcontroller o ther technical issues 5- 5 vector_init_block ldr pc, reset_addr ldr pc, undefined_addr ldr pc, swi_addr ldr pc, prefetch_addr ldr pc, abort_addr nop ldr pc, irq_addr ldr pc, fiq_addr reset_addr dcd reset_handler undefined_addr dcd systemundefinedhandler swi_addr dcd systemswihandler prefetch_addr dcd systemprefetchhandler abort_addr dcd systemaborthandler dcd 0 ; reserved vector irq_addr dcd systemirqhandler fiq_addr dcd systemfiqhandler endif area main, code, re adonly ;========================================================== ; the reset entry point ;========================================================== reset_handler ;/* reset entry point */ ;===================================== ; led display ;===================================== ldr r1, =iopmod ldr r0, =0xff str r0, [r1] ldr r1, =iopdata ldr r0, =0x55 str r0, [r1] ;===================================== ; setup special register ;=================================== == ldr r0, =0x3ff0000 ; read syscfg register value ldr r1,[r0] ; to idetify dram type ldr r2, =0x80000000 and r0, r1, r2 ; mask dram type mode bit cmp r0, r2 bne edo_dram_configuration b sync_dram_configuration ; only when ks32c50100 ;================================================== ; special register configuration for edo mode dram ; when KS32C5000 and ks32c50100
other technical issues ks32c50100/5000a risc microcontroller 5- 6 ;================================================== edo_dram_configuration ldr r0, =0x3ff0000 ldr r1, =0 x3ffff90 ; setvalue = 0x3ffff91 str r1, [r0] ; cache,wb disable ; start_addr = 0x3ff00000 ;rom and ram configuration(multiple load and store) adrl r0, systeminitdata ldmia r0, {r1-r12} ldr r0, =0x3ff0000 + 0x3010 ; romcntr offset : 0x3010 stmia r0, {r1-r12} ldr r1,=dram_base str r1,[r1] ; [dram_base] = dram_base ldr r2,[r1] ; read dram data cmp r2,r1 bne sync_dram_configuration ;======================================================= ====== ; copy rom image to edo dram, change rom and dram base pointer ;============================================================= rom2dram_copy_start ldr r0, =|image$$ro$$base| ; get pointer to rom data ldr r1, =|image$$rw$$limit| ; and ram copy ldr r2, =dram_base ; copy dram area base sub r1, r1, r0 ; [r1] is loop count add r1, r1, #4 ; [r1] is loop count rom2dram_copy_loop ldr r3, [r0], #4 str r3, [r2], #4 subs r1, r1, #4 ; down count bne rom2dram_copy_loop ;==================================== ; change base address of rom and dram ;==================================== adrl r0, systeminitdata_s ldmia r0, {r1-r12} ldr r0, =0x3ff0000 + 0x3010 ; romcntr offset : 0x3010 stmia r0, {r1-r12} b initialize_stack ;================================================== ; special register configuration for sync dram ; only when ks32c50100 ;================================================== sync_dram_configuration ldr r0, =0x3ff0000 ldr r1, =0x83ffff90 ; setvalue = 0x83ffff91 str r1, [r0] ; cache,wb disable
ks32c50100/5000a risc microcontroller o ther technical issues 5- 7 ; start_addr = 0x3ff00000 ;rom and ram configuration(multiple load and store) adrl r0, systeminitdatasdram ldmia r0, {r1-r12} ldr r0, =0x3ff0000 + 0x3010 ; romcntr offset : 0x3010 stmia r0, {r1-r12} ;============================================================== ; copy rom image to sync dram, change rom and dram base pointer ;============================================================== rom2sdram_copy_start ldr r0, =|image$$ro$$base| ; get pointer to rom data ldr r1, =|image$$ro$$limit| ; and ram copy ldr r2, =dram_base ; copy dram area base sub r1, r1, r0 ; [r1] is loop count add r1, r1, #4 ; [r1] is loop count rom2sdram_copy_loop ldr r3, [r0], #4 str r3, [r2], #4 subs r1, r1, #4 ; down count bne rom2sdram_copy_loop ;==================================== ; change base address of rom and dram ;==================================== adrl r0, systemini tdatasdram_s ldmia r0, {r1-r12} ldr r0, =0x3ff0000 + 0x3010 ; romcntr offset : 0x3010 stmia r0, {r1-r12} ;===================================== ; initialise stack ;===================================== initialize_stack mrs r0, cpsr bic r0, r0, #lockout | mode_mask orr r2, r0, #usr_mode orr r1, r0, #lockout | fiq_mode msr cpsr, r1 msr spsr, r2 ldr sp, =fiq_stack orr r1, r0, #lockout | irq_mode msr cpsr, r1 msr spsr, r2 ldr sp, =irq_stack orr r1, r0, #lockout | abt_mode msr cpsr, r1 msr spsr, r2
other technical issues ks32c50100/5000a risc microcontroller 5- 8 ldr sp, =abt_stack orr r1, r0, #lockout | udf_mode msr cpsr, r1 msr spsr, r2 ldr sp, =udf_stack orr r1, r0, #lockout | sup_mode msr cpsr, r1 msr spsr, r2 ldr sp, =sup_stack ; change cpsr to svc mode ;===================================== ; initialise memory required by c code ;===================================== ldr r0, =|image$$ro$$limit| ; get pointer to rom data ldr r1, =|image$$rw$$base| ; and ram copy ldr r3, =|image$$zi$$base| ; zero init base => top of initialised data cmp r0, r1 ; check that they are different beq %1 0 cmp r1, r3 ; copy init data ldrcc r2, [r0], #4 strcc r2, [r1], #4 bcc %0 1 ldr r1, =|image$$zi$$limit| ; top of zero init segment mov r2, #0 2 cmp r3, r1 ; zero init strcc r2, [r3], #4 bcc %2 ;==================================================== ; now change to user mode and set up user mode stack. ;== ================================================== mrs r0, cpsr bic r0, r0, #lockout | mode_mask orr r1, r0, #usr_mode msr cpsr, r0 ldr sp, =usr_stack ; /* call c_entry application routine with a pointer to the first */ ; /* available memory address after ther compiler's global data */ ; /* this memory may be used by the application. */ ;=========================== ; now we enter the c program ;=========================== import c_entry bl c_entry ;=========================================== ; exception vector function definition ; consist of function call from c-program. ;===========================================
ks32c50100/5000a risc microcontroller o ther technical issues 5- 9 systemundefinedhandler import isr_undefhandler stmfd sp!, {r0-r12} b isr_undefhandler ldmfd sp!, {r0-r12, pc}^ systemswihandler stmfd sp!, {r0-r12,lr} ldr r0, [lr, #-4] bic r0, r0, #0xff000000 cmp r0, #0xff beq makesvc ldmfd sp!, {r0-r12, pc}^ makesvc mrs r1, spsr bic r1, r1, #mode_mask orr r2, r1, #sup_ mode msr spsr, r2 ldmfd sp!, {r0-r12, pc}^ systemprefetchhandler import isr_prefetchhandler stmfd sp!, {r0-r12, lr} b isr_prefetchhandler ldmfd sp!, {r0-r12, lr} ;add sp, sp, #4 subs pc, lr, #4 systemaborthandler import isr_aborthandler stmfd sp!, {r0-r12, lr} b isr_aborthandler ldmfd sp!, {r0-r12, lr} ;add sp, sp, #4 subs pc, lr, #8 systemreserv subs pc, lr, #4 systemirqhandler import isr_irqhandler stmfd sp!, {r0-r12, lr} bl isr_irqhandler ldmfd sp!, {r0-r12, lr} subs pc, lr, #4 systemfiqhandler import isr_fiqhandler stmfd sp!, {r0-r7, lr} bl isr_fiqhandler ldmfd sp!, {r0-r7, lr} subs pc, lr, #4
other technical issues ks32c50100/5000a risc microcontroller 5- 10 area romdata, data, readonly ;====================================================== ; dram system initialize data(KS32C5000 and ks32c50100) ;====================================================== systeminitdata dcd rextdbwth ; dram1(half), rom5(byte), rom1(half), else 32bit dcd rromcon0 ; 0x0000000 ~ 0x01fffff, rom0,4mbit,2cycle dcd rromcon1 ; dcd rromcon2 ; 0x0400000 ~ 0x05fffff, rom2 dcd rromcon3 ; 0x0600000 ~ 0x07fffff, rom3 dcd rromcon4 ; 0x0800000 ~ 0x09fffff, rom4 dcd rromcon5 ; dcd rdramcon0 ; 0x1000000 ~ 0x13fffff, dram0 4m, dcd rdramcon1 ; 0x1400000 ~ 0x17fffff, dram1 4m, dcd rdramcon2 ; 0x1800000 ~ 0x1efffff, dram2 16m dcd rdramcon3 ; 0x1c00000 ~ 0x1ffffff dcd rrefextcon ; external i/o, refresh systeminitdata_s dcd rextdbwth ; dram1(half), rom5(byte), rom1(half), else 32bit dcd rromcon0_s ; 0x1 000000 ~ 0x11fffff, rom0,4mbit,2cycle dcd rromcon1_s ; 0x1200000 ~ 0x13fffff, rom0 dcd rromcon2_s ; 0x1400000 ~ 0x15fffff, rom2 dcd rromcon3_s ; 0x1600000 ~ 0x17fffff, rom3 dcd rromcon4_s ; 0x1800000 ~ 0x19fffff, rom4 dcd rromcon5_s ; 0x1a00000 ~ 0x1bfffff, rom4 dcd rdramcon0_s ; 0x0000000 ~ 0x03fffff, dram0 dcd rdramcon1_s ; 0x0400000 ~ 0x07fffff, dram1 dcd rdramcon2_s ; 0x0800000 ~ 0x0efffff, dram2 dcd rdramcon3_s ; 0x0c00000 ~ 0x0ffffff dcd rrefextcon ; external i/o, refresh ;====================================================== ; sdram system initialize data (ks32c50100 only) ;====================================================== systeminitdatasdram dcd rextdbwth ; dram1(half), rom5(byte), rom1(half), else 32bit dcd rromcon0 ; 0x0000000 ~ 0x01fffff, rom0,4mbit,2cycle dcd rromcon1 ; dcd rromcon2 ; 0x0400000 ~ 0x05fffff, rom2 dcd rromcon3 ; 0x0600000 ~ 0x07fffff, rom3 dcd rromcon4 ; 0x0800000 ~ 0x09fffff, rom4 dcd rromcon5 ; dcd rsdramcon0 ; 0x1000000 ~ 0x13fffff, dram0 4m, dcd rsdramcon1 ; 0x1400000 ~ 0x17fffff, dram1 4m, dcd rsdramcon2 ; 0x1800000 ~ 0x1efffff, dram2 16m dcd rsdramcon3 ; 0x1c00000 ~ 0x1ffffff dcd rsrefextcon ; external i/o, refresh systeminitdatasdram_s dcd rextdbwth ; dram1(half), rom5(byte), rom1(half), else 32bit
ks32c50100/5000a risc microcontroller o ther technical issues 5- 11 dcd rromcon0_s ; 0x1000000 ~ 0x11fffff, rom0,4mbit,2cycle dcd rromcon1_s ; dcd rromcon2_s ; 0x1400000 ~ 0x15fffff, rom2 dcd rromcon3_s ; 0x1600000 ~ 0x17fffff, rom3 dcd rromcon4_s ; 0x1800000 ~ 0x19fffff, rom4 dcd rromcon5_s ; dcd rsdramcon0_s ; 0x0000000 ~ 0x03fffff, dram0 4m, dcd rsdramcon1_s ; 0x0400000 ~ 0x07fffff, dram1 4m, dcd rsdramcon2_s ; 0x0800000 ~ 0x0efffff, dram2 16m dcd rsdramcon3_s ; 0x0c00000 ~ 0x0ffffff dcd rsrefextcon ; external i/o, refresh align ;/***************************************************/ area sys_stack, noinit ;/***************************************************/ % usr_stack_size usr_stack % udf_stack_size udf_stack % abt_stack_size abt_stack % irq_stack_size irq_stack % fiq_stack_size fiq_stack % sup_stack_size sup_stack ;/***************************************************/ end when use dram as boot area, then you also need to modify the ? snds.a ? file. this file define the memory controller base and end pointer, the source code of ? snds.a ? is listed listing 5-2. listing 5-2. memory control value definition (snds.a) ;------------------------------------------------------------- some code omitted for readibility ;/* -> romcon0 : rom bank0 control register */ ;------------------------------------------------------------- rombaseptr0 equ 0x000:shl:10 ;=0x0000000 ; normal mode romendptr0 equ 0x020:shl:20 ;=0x0200000 ; normal mode rombaseptr0_s equ 0x100:shl:10 ;=0x1000000 romendptr0_s equ 0x120:shl:20 ;=0x1200000 pmc0 equ 0x0 ; 0x0=normal rom, 0x1=4word page ; 0x2=8word page, 0x3=16word page rtpa0 equ (0x0:shl:2) ; 0x0=5cycle, 0x1=2cycle
other technical issues ks32c50100/5000a risc microcontroller 5- 12 ; 0x2=3cycle, 0x3=4cycle rtacc0 equ (0x6:shl:4) ; 0x0=disable, 0x1=2cycle ; 0x2=3cycle, 0x3=4cycle ; 0x4=5cycle, 0x5=6cycle ; 0x6=7cycle, 0x7=reserved rromcon0 equ romendptr0+rombaseptr0+rtacc0+rtpa0+pmc0 rromcon0_s equ romendptr0_s+rombaseptr0_s+rtacc0+rtpa0+pmc0 ;------------------------------------------------------------- some code omitted for readibility ;/* -> dramcon0 : ram bank0 control register */ ;------------------------------------------------------------- edo_mode0 equ 1 ;(edo)0=normal, 1=edo dram casprechargetime0 equ 1 ;(tcp)0=1cycle,1=2cycle casstrobetime0 equ 3 ;(tcs)0=1cycle ~ 3=4cycle dramcon0reserved equ 1 ; must be set to 1 ras2casdelay0 equ 1 ;(trc)0=1cycle,1=2cycle rasprechargetime0 equ 3 ;(trp)0=1cycle ~ 3=4clcyle drambaseptr0 equ 0x100:shl:10 ;=0x1000000 dramendptr0 equ 0x140:shl:20 ;=0x1400000 drambaseptr0_s equ 0x000:shl:10 ;=0x0000000 dramendptr0_s equ 0x040:shl:20 ;=0x0400000 nocolumnaddr0 equ 2 ;0=8bit,1=9bit,2=10bit,3=11bits ;------------------------------------------------------------- tcs0 equ casstrobetime0:shl:1 tcp0 equ casprechargetime0:shl:3 dumy0 equ dramcon0reserved:shl:4 ; dummy cycle trc0 equ ras2casdelay0:shl:7 trp0 equ rasprechargetime0:shl:8 can0 equ nocolumnaddr0:shl:30 rdramcon0 equ can0+dramendptr0+drambaseptr0+tr p0+trc0+tcp0+tcs0+dumy0+edo_mode0 rdramcon0_s equ can0+dramendptr0_s+drambaseptr0_s+trp0+trc0+tcp0+tcs0+dumy0+edo_mode0 ;---------------------------------------------------------------------------------- sras2casdelay0 equ 1 ;(trc)0=1cycle,1=2cycle srasprechargetime0 equ 3 ;(trp)0=1cycle ~ 3=4clcyle snocolumnaddr0 equ 0 ;0=8bit,1=9bit,2=10bit,3=11bits scan0 equ snocolumnaddr0:shl:30 strc0 equ sras2casdelay0:shl:7 strp0 equ srasprechargetime0:shl:8 ; rsdramcon0 equ scan0+dramendptr0+drambaseptr0+strp0+strc0 rsdramcon0_s equ scan0+dramendptr0_s+drambaseptr0_s+strp0+strc0 ;-------------------------------------------------------------
ks32c50100/5000a risc microcontroller o ther technical issues 5- 13 exception handling when use dram as boot area when use dram as boot area, the exception handle routine is easy to implement. at the original diagnostic code use dram base pointer as exception handler area, but when you use dram as boot area, you only need the exception vector area to going into interrupt service routine. the exception handle routine is depicted in figure 5-3. this figure show the exception handling routine example with irq exception. reset_handler undefined_handler swi_handler prefetch_handler abort_handler reserved irq_handler fiq_handler 0x0 0x4 0x8 0xc 0x10 0x14 0x18 0x1c usercodearea systemundefinedhandler systemswihandler systemprefetchhandler systemaborthandler systemreserv systemirqhandler systemfiqhandler ~ void isr_irqhandler( void) { intoffset=(u32)intoffset; clear_pendingbit(intoffset>>2) ; (*interrupthandlers[intoffset>>2])(); } ~ systemirqhandler import isr_irqhandler stmfd sp!, {r0-r12, lr} bl i s r_irqhandler ldmfd sp!, {r0-r12, lr} subs pc, lr, #4 =usercodearea stack area user area dram base pointer dram user code area sp_irq directly point the exception handler routine =usercodearea figure 5-3. exception handling process when use dram as boot area
other technical issues ks32c50100/5000a risc microcontroller 5- 14 how to debug snds100 using emulator without boot rom? you can evaluate snds100 board using circuit emulator(ex, embeddedice) without boot rom. but, to do this, you have to consider two points. one is the side of hardware consideration and the other is software consideration. that is due to the reset circuit(nreset, ntrst) problem of netmcu device. snds100 reset circuit have to be revised which is refered to ? section 4. system design : figure 4-28 embededice interface design example ? . this is came from the without boot rom. after the power on reset or key reset, rom bank0 will be located at address zero by default reset system memory map but there is no boot rom. so, you have to re-map the system default memory map before downloading the application. this memory map can be changed by call initial map file at adw ? s command window.(arm debuger window). hardware consideration it is the main problem of invoking adw (arm debugger) after resetting snds100 board that swi interrupts the downloading of a debugging program . we find out that ntrst(62-th pin : pull-up internally) is needed to be floated. just cutting the pattern connected to ntrst pin in snds100 board , you can invoke adw and download a program without any problem and without considering time interval. (see, figure 4-28). software consideration after modifying snds100 board , you can go to the next step as following flow. ? making a debugging image file ? invoking adw ? setting the special registers of KS32C5000 series and adw for debugging. ? downloading image file. ? step into debugging mode the downloaded program will start and you can debug your program with the adw.
ks32c50100/5000a risc microcontroller o ther technical issues 5- 15 making a debugging image file you need to modify files concerning memory configuration and interrupt handling. these are init.s, memory.a and makefile modifying memory.a and snds.a some value related to memory configuration should be changed in a pre-distributed memory. a file. ? dram_base symbol value ? (this means downloading start area, it is distinguished form booting code we tried) dram_base equ 0x1000000 (old) dram_base equ 0x300000 (new) ? system user area ^ dram_base+exceptionsize ; ; ^ 0x1000050 (old ) ; ^ 0x300050 ; (new) only one symbol is needed to be changed for snds.a dram_ base equ 0x1000000 (old) dram_base equ 0x300000 (new) modifying init.s inis.s file is simplified only for downloading dram. the main difference from pre-distributed one is that memory initialized (systeminitdata symbol) part is removed. part 2.3 setting special register for ks32c50100 will explain how to replace this role . and we overwrite irq_handler address at 0x18 address and fiq_handler address at 0x1c address for interrupt mapping . this may corrupt a debugging information , but it will is correspond to only debug starting information. so you can keep debugging with adw without regarding this. listing 5-3. modifying init.s get memory.a get snds.a area init, code, readonly ; --- define entry point export __main ; defined to ensure that c runtime system __main ; is not linked in entry b reset_handler b undefined_handler b swi_handler b prefetch_handler b abort_handler nop ; reserved v ector b irq_handler b fiq_handler
other technical issues ks32c50100/5000a risc microcontroller 5- 16 ;========================================================== ; the default exception handler vector entry pointer setup ;========================================================== nop fiq_handler sub sp, sp, #4 stmfd sp!, {r0} ldr r0, =handlefiq ldr r0, [r0] str r0, [sp, #4] ldmfd sp!, {r0, pc} irq_handler sub sp, sp, #4 stmfd sp!, {r0} ldr r0, =handleirq ldr r0, [r0] str r0, [sp, #4] ldmfd sp!, {r0, pc} prefetch_handler sub s p, sp, #4 stmfd sp!, {r0} ldr r0, =handleprefetch ldr r0, [r0] str r0, [sp, #4] ldmfd sp!, {r0, pc} abort_handler sub sp, sp, #4 stmfd sp!, {r0} ldr r0, =handleabort ldr r0, [r0] str r0, [sp, #4] ldmfd sp!, {r0, pc} undefined_handler sub sp, sp, #4 stmfd sp!, {r0} ldr r0, =handleundef ldr r0, [r0] str r0, [sp, #4] ldmfd sp!, {r0, pc} swi_handler sub sp, sp, #4 stmfd sp!, {r0} ldr r0, =handleswi ldr r0, [r0] str r0, [sp, #4] ldmfd sp!, {r0, pc} area main, code, readonly ;===================================== ; the reset entry point ;===================================== reset_handler
ks32c50100/5000a risc microcontroller o ther technical issues 5- 17 ;===================================== ; initialise stack ;===================================== initialize_stack mrs r0, cpsr bic r0, r0, #lockout | mode_mask orr r2, r0, #usr_mode orr r1, r0, #lockout | fiq_mode msr cpsr, r1 msr spsr, r2 ldr sp, =fiq_stack orr r1, r0, #lockout | irq_mode msr cpsr, r1 msr spsr, r2 ldr sp, =irq_stack orr r1, r0, #lockout | abt_mode msr cpsr, r1 msr spsr, r2 ldr sp, =abt_stack orr r1, r0, #lockout | udf_mode msr cpsr, r1 msr spsr, r2 ldr sp, =udf_stack orr r1, r0, #lockout | sup_mode msr cpsr, r1 msr spsr, r2 ldr sp, =sup_stack ; change cpsr to svc mode ;===================================== ; led display ;===================================== ldr r1, =iopmod ldr r0, =0xff str r0, [r1] ldr r1, =iopdata ldr r0, =0x55 str r0, [r1] ;===================================== ; uart setup for console ; 38400, data= 8 bits , stop = 1 bits ;===================================== ldr r1, =uartlcon0 ldr r0, =0x43 str r0,[r1] ldr r1, =uartcont0 ldr r0, =0x9 str r0,[r1] ldr r1, =uartbrd0 ; ldr r0, =0x280 ; 38400 bps for 50mhz ; ldr r0, =0x350 ; 38400 bps for 33mhz ldr r0, =0x2f0 ; 38400 bps for 29.4912mhz ; ;ldr r0, =0x160 ; 38400 bps for 14.31818mhz str r0,[r1]
other technical issues ks32c50100/5000a risc microcontroller 5- 18 ; print out boot up banner to console ldr r0, =bootupbanner0 bl printstring ; main memory test (post) ldr r0, =drampoststart bl pri ntstring ;================================================== ; special register configuration for edo mode dram ;================================================== b exception_vector_table_setup ;================================================== ; special register configuration for sync dram ;================================================== ;============================= ; exception vector table setup ;============================= exception_vector_table_setup ldr r0, =handlereset ; exception vecto r table memory loc. ldr r1, =exceptionhandlertable ; exception handler assign mov r2, #8 ; number of exception is 8 exceptloop ldr r3, [r1], #4 str r3, [r0], #4 subs r2, r2, #1 ; down count bne exceptloop ;===================================== ; initialise memory required by c code ;===================================== import |image$$ro$$limit| ; end of rom code (=start of rom data) import |image$$rw$$base| ; base of ram to initialise import |image$$zi$$base| ; base and li mit of area import |image$$zi$$limit| ; to zero initialise ldr r0, =|image$$ro$$limit| ; get pointer to rom data ldr r1, =|image$$rw$$base| ; and ram copy ldr r3, =|image$$zi$$base| ; zero init base => top of initialised data cmp r0, r1 ; check that they are different beq %1 0 cmp r1, r3 ; copy init data ldrcc r2, [r0], #4 strcc r2, [r1], #4 bcc %0 1 ldr r1, =|image$$zi$$limit| ; top of zero init s egment mov r2, #0 2 cmp r3, r1 ; zero init strcc r2, [r3], #4 bcc %2 ;==================================================== ; now change to user mode and set up user mode stack. ;==================================================== mrs r0, cpsr bic r0, r0, #lockout | mode_mask orr r1, r0, #usr_mode msr cpsr, r0 ldr sp, =usr_stack ; /* call c_entry application routine with a pointer to the first */
ks32c50100/5000a risc microcontroller o ther technical issues 5- 19 ; /* available memory address after ther compiler's global data */ ; /* this memory may be used by the application. */ ;=========================== ; now we enter the c program ;=========================== ldr r0, =0x98 ldr r1, =0x18 ldr r2, [r0] str r2, [r1] ; this is for irq_handler ldr r0, =0x9c ldr r1, =0x1c ldr r2, [r0] str r2, [r1] ; this is for fiq_handler import c_entry bl c_entry ;=========================================== ; exception vector function definition ; consist of function call from c-program. ;=========================================== systemundefinedhandler import isr_undefhandler stmfd sp!, {r0-r12} b isr_undefhandler ldmfd sp!, {r0-r12, pc}^ systemswihandler stmfd sp!, {r0-r12,lr} ldr r0, [lr, #-4] bic r0, r0, #0xff000000 cmp r0, #0xff beq makesvc ldmfd sp!, {r0-r12, pc}^ makesvc mrs r1, spsr bic r1, r1, #mode_mask orr r2, r1, #sup_mode msr spsr, r2 ldmfd sp!, {r0-r12, pc}^ systemprefetchhandler import isr_prefetchhandler stmfd sp!, {r0-r12, lr} b is r_prefetchhandler ldmfd sp!, {r0-r12, lr} ;add sp, sp, #4 subs pc, lr, #4 systemaborthandler import isr_aborthandler stmfd sp!, {r0-r12, lr} b isr_aborthandler ldmfd sp!, {r0-r12, lr} ;add sp, sp, #4 subs pc, lr, #8 systemreserv
other technical issues ks32c50100/5000a risc microcontroller 5- 20 subs pc, lr, #4 systemirqhandler import isr_irqhandler stmfd sp!, {r0-r12, lr} bl isr_irqhandler ldmfd sp!, {r0-r12, lr} subs pc, lr, #4 systemfiqhandler import isr_fiqhandler stmfd sp!, {r0-r7, lr} bl isr_fiqhandler ldmfd sp!, {r0-r7, lr} subs pc, lr, #4 ;====================================================== ; utility section ; print a zero terminated string ;====================================================== printstring mov r4, lr mov r5, r0 01 ldrb r1, [r5],#1 ; read byte( one character) and r0,r1, #&ff tst r0, #&ff moveq pc, r4 ; if 0, return. bl putbyte b %b01 putbyte putbyteloop ldr r3,=uartstat0 ldr r2,[r3] tst r2,#&40 ; uart_stat_xmit_empty ? beq putbyteloop ldr r3,=uarttxh0 str r0,[r3] ; write t o thr mov pc,lr area romdata, data, readonly ;=========================================== ; exception handler vector table entry point ;=========================================== exceptionhandlertable dcd usercodearea dcd systemundefinedhandler dcd systemswihandler dcd systemprefetchhandler dcd systemaborthandler dcd systemreserv dcd systemirqhandler dcd systemfiqhandler align bootupbanner0 dcb &a,&d,&a,&d,"$$$ snds100 boot-up dialog !!!",0 drampoststart dcb &a,&d,"$$$ snds100 dram post => ",0 drampostfinish dcb "mb installed !",0 cacheenablebanner dcb &a,&d," $$$ 8k cache is enabled !",0 ;/***************************************************/
ks32c50100/5000a risc microcontroller o ther technical issues 5- 21 area sys_stack, noinit ;/***************************************************/ % usr_stack_size usr_stack % udf_stack_size udf_stack % abt_stack_size abt_stack % irq_stack_size irq_stack % fiq_stack_size fiq_stack % sup_stack_size sup_stack ;/***************************************************/ end modifying makefile you should map code area to address 0x0 and r/w area to a reasonable address below dram_base. the following list shows the way to modify a makefile . listing 5-4. makefile toolpath = c:\arm211a\bin link = $(toolpath)\armlink asm = $(toolpath)\armasm cc = $(toolpath)\armcc lib = c:\arm211a\lib\armlib.32b asmflag1 = -bi -g -apcs 3/32bit cflags = -bi -c -fc -g -apcs 3/32bit -processor arm 7tm -arch 4t ## >> when code down load to dram asmflag3 = -bi -apcs 3/32bit -g -pd "rom_at_address_zero setl {true}" linkflag4 = -first init.o(init) -ro 0x0 -rw 0x200000 -o diag.axf -aif -debug -symbols diag.sym $(objs) $(lib) objs = init.o start.o diag.o yours.o diag.axf: $(objs) $(link) $(linkflag4) init.o: init.s $(asm) $(asmflag3) init.s -o init.o -list init.lst start.o: start.s $(asm) $(asmflag1) start.s -o start.o diag.o: diag.c $(cc) $(cflags) -errors diag.err diag. c yours.o: yours.c $(cc) $(cflags) -errors yours.err yours.c after modifying makefile , type c:\> armmake diag.axf to get debugging image file. invoking adw if you modify snds100 board , adw can be invoked without considering the elapsed time.
other technical issues ks32c50100/5000a risc microcontroller 5- 22 setting the special registers of KS32C5000 series your write a text file to write special registers. your write a text file to write special registers. when using edo or fast page dram ( armdram.ini at c root directory ) let 0x3ff3010 = 0xfffffffa let 0x3ff3014 = 0x12040060 let 0x3ff3018 = 0x14042060 let 0x3ff301c = 0x16044060 let 0x3ff3020 = 0x18046060 let 0x3ff3024 = 0x1a048060 let 0x3ff3028 = 0x1c04a060 let 0x3ff302c = 0x8400039b let 0x3ff3030 = 0x0601039b let 0x3ff3034 = 0x0801439b let 0x3ff3038 = 0x0a01839b let 0x3ff303c = 0xce378360 when using sync dram ( armsdram.ini at c root directory ) let 0x3ff0000 = 0x87ffff91 let 0x3ff3010 = 0xfffffffa let 0x3ff3014 = 0x12040060 let 0x3ff3018 = 0x14042060 let 0x3ff301c = 0x16044060 let 0x3ff3020 = 0x18046060 let 0x3ff3024 = 0x1a048060 let 0x3ff3028 = 0x1c04a060 let 0x3ff302c = 0x04000380 let 0x3ff3030 = 0x0601039b let 0x3ff3034 = 0x0801439b let 0x3ff3038 = 0x0a01839b let 0x3ff303c = 0xce338360 after making text file , give a command ( obey c:\armsdram.ini) at adw command window. then adw initial KS32C5000 series system manager registers for interfacing with sdram. after this step , you have finished the preparation to download a image. selecting image file and setting adw for debugging select file menu bar and load image menu and get your image file.then type obey c:\armsd.ini (see programmer ? s guide section 2.). step into debugging. after doing all of previous work , you can run into debugging with code at dram based 0x0.

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